NOVEL QUANTUM COMPRESSOR DESIGNS USING NEW GENETIC ALGORITHM-BASED SIMULATOR, ANALYZER AND SYNTHESIZER SOFTWARE IN NANOTECHNOLOGY

2010 ◽  
Vol 08 (07) ◽  
pp. 1219-1231 ◽  
Author(s):  
MAJID HAGHPARAST ◽  
MAJID MOHAMMADI
Keyword(s):  
Genetic Algorithm ◽  
Quantum Computing ◽  
Optical Computing ◽  
Logic Circuits ◽  
Basic Block ◽  
Quantum Cost ◽  
Cmos Design ◽  
Low Power Cmos ◽  
First Time ◽  
Better Than

Quantum and reversible logic circuits have found emerging attentions in nanotechnology, optical computing, quantum computing, and low power CMOS design. In this paper, we propose some new quantum and reversible compressors using our new genetic algorithm-based simulator, analyzer, and synthesizer software. The proposed quantum 4:2 and 6:2 compressor circuits are compared with the existing counterparts in terms of number of constant inputs, number of garbage outputs, delay and the quantum cost (QC). We have also designed quantum 7:2 compressor for the first time. The proposed quantum compressors are optimized in terms of QC and delay. The proposed designs can be used as a basic block in complex systems like multipliers, and can execute complicated operations better than the existing designs in literature.

OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT

2009 ◽  
Vol 18 (02) ◽  
pp. 311-323 ◽  
Author(s):  
MAJID HAGHPARAST ◽  
MAJID MOHAMMADI ◽  
KEIVAN NAVI ◽  
MOHAMMAD ESHGHI
Keyword(s):  
Dna Computing ◽  
Full Adder ◽  
Logic Circuits ◽  
Optical Information ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Cmos Design ◽  
Fair Comparison ◽  
Low Power Cmos ◽  
Significant Attention

Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.

Efficient designs of reversible BCD to EX-3 Converter with low quantum cost in nanoscale

2020 ◽  
Vol 18 (05) ◽  
pp. 2050020 ◽  
Author(s):  
Mojtaba Noorallahzadeh ◽  
Mohammad Mosleh
Keyword(s):  
Quantum Computing ◽  
Optical Computing ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Computing Systems ◽  
Gate Count ◽  
Reversible Gate ◽  
Significant Research ◽  
Research Domain ◽  
Better Than

As an interesting and significant research domain, reversible logic is massively utilized in technologies, including optical computing, cryptography, quantum computing, nanotechnology, and so on. The realization of quantum computing is not possible without the implementation of reversible logic, and reversible designs are presented mainly to minimize the thermal loss because of the data input bits lost in the irreversible circuit. Digital converters, as the most important logic circuits, are used to connect computing systems with different binary codes. This paper first proposes a new reversible gate called Reversible Noorallahzadeh[Formula: see text]Mosleh Gate (RNMG). Then, using the proposed RNMG gate as well as existing NMG1, NMG6, and PG gates, three different designs of reversible Binary-Coded Decimal (BCD) to EX-3 code converter are proposed. Our results indicate that the proposed BCD to EX-3 code converters are superior to previous designs in terms of quantum cost. Moreover, the proposed converters are comparable or better than previous designs in terms of gate count, constant inputs, and garbage outputs.

scholarly journals A Review on Reversible Computing and it’s applications on combinational circuits

2021 ◽  
Vol 9 (6) ◽  
pp. 806-814
Keyword(s):  
Quantum Computing ◽  
Optical Computing ◽  
Digital Signal ◽  
Vital Role ◽  
Literature Survey ◽  
Quantum Cost ◽  
Combinational Circuits ◽  
Reversible Computing ◽  
Low Power Cmos ◽  
Design Challenge

In this era of nanometer semiconductor nodes, the transistor scaling and voltage scaling are not any longer in line with each other, leading to the failure of the Dennard scaling. Thus, it poses a severe design challenge. Reversible computing plays a vital role in applications like low power CMOS, nanotechnology, quantum computing, optical computing, digital signal processing, cryptography, computer graphics andmany more. The primary reasons for designing reversible logic are diminishing the quantum cost, profundity of the circuits and the garbage outputs. It is impossible to determine the quantum computing without implementing the reversible computation. This paper will represent the literature survey based on several papers on combinational circuits using reversible computing and also the future scope is to be discussed.

Design Approaches for Resource and Performance Optimization of Reversible BCD Addition and Unified BCD Addition/Subtraction Circuits

2017 ◽  
Vol 27 (03) ◽  
pp. 1850048
Author(s):  
H. V. Jayashree ◽  
Sharan Patil ◽  
V. K Agrawal
Keyword(s):  
Quantum Computing ◽  
Performance Optimization ◽  
Optical Computing ◽  
Performance Parameters ◽  
Nano Technology ◽  
Reversible Circuits ◽  
Cmos Design ◽  
Low Power Cmos ◽  
And Performance ◽  
Subtraction Circuit

The world of computing is in transition. As chips become smaller and faster, they dissipate more heat, in turn more energy is consumed. Reversible logic is gaining significance in the context of emerging technologies such as quantum computing. Reversible circuits have one-to-one mapping between the inputs and outputs. Hence, there is no loss of energy. Reversible circuits are of high interest in low-power CMOS design, optical computing, nano technology, and quantum computing. In this work, we present designs of reversible Binary Coded Decimal (BCD) adder and unified reversible BCD addition/subtraction circuit. We propose three design approaches for BCD addition. The proposed designs 1 and 2 are aimed at optimizing Garbage Outputs. The proposed design 3 outperforms in all the performance parameters along with producing zero Garbage Outputs compared to proposed designs 1 and 2. We present [Formula: see text] digit reversible BCD addition/subtraction circuit using proposed design 3 for BCD addition to get the benefit of performance parameter optimization. This design outperforms existing counterparts.

NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS

2011 ◽  
Vol 09 (02) ◽  
pp. 723-738 ◽  
Author(s):  
MAJID HAGHPARAST ◽  
KEIVAN NAVI
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Quantum Cost ◽  
Hamming Code ◽  
Code Generator ◽  
Flip Flop ◽  
Cmos Design ◽  
Error Coding ◽  
Error Detector ◽  
First Time

Reversible logic is an emerging area of research, having applications in nanotechnology, low power CMOS design, quantum computing, and DNA computing. In this paper, two different parity-preserving reversible error coding and detection circuits are studied. First we propose two new reversible Hamming code generator circuits. One of them is parity-preserve. We also propose a new parity-preserving reversible Hamming code error detector circuit. The proposed parity-preserving reversible Hamming code generator (PPHCG) and error detector circuits provide single error correction–double error detection (SEC–DED). The designs are better than the existing counterparts in terms of quantum cost (QC), number of constant inputs, and number of garbage outputs. Then we propose parity-preserving reversible cyclic code encoder/decoder circuits for the first time. A parity-preserving reversible D flip-flop is also proposed. Equivalent quantum representation of two parity-preserving 4 ∗ 4 reversible gates, IG, and PPHCG, are also proposed. We show for the first time that IG has a QC of only 7 and PPHCG has a QC of only 6.

scholarly journals An improved design of reversible adder/subtractor

2018 ◽  
Vol 7 (2.12) ◽  
pp. 182
Author(s):  
Gowthami P ◽  
R V. S. Satyanarayana
Keyword(s):  
Quantum Computing ◽  
Dna Computing ◽  
Optical Computing ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Improved Design

Reversible logic has gained an importance in the fields such as Quantum computing, DNA computing, Bio informatics, Nanotechnology and Optical computing etc. This paper presents a new design of reversible adder/subtractor circuit. The proposed design has better performance than the existing counterpart in terms of reversible gates, garbage outputs and quantum cost. 

scholarly journals A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic

2015 ◽  
Vol 11 (2) ◽  
pp. 104
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Reversible Logic ◽  
Low Loss ◽  
Arithmetic Logic Unit ◽  
Novel Approach ◽  
Cmos Design ◽  
Binary Arithmetic ◽  
Low Power Cmos ◽  
Logic Unit

Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) using optimized 8:1 multiplexer circuit with reversible logic concept [1]. This ALU circuit can perform complement, transfer, addition, subtraction, multiplication, OR, XOR, NAND functions on given values. The ALU circuit has been simulated on Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. This 2-bit ALU using reversible logic is useful for the designs of low power loss systems.

Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach

2015 ◽  
Vol 4 (3) ◽  
pp. 213
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Reversible Logic ◽  
Optimized Design ◽  
Storage Unit ◽  
Computing Device ◽  
Cmos Design ◽  
Low Power Cmos ◽  
Logic Approach

Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.

scholarly journals Effect of Antibacterial Root Canal Sealer on Persistent Apical Periodontitis

Antibiotics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 741
Author(s):  
Zheng Wang ◽  
Ge Yang ◽  
Biao Ren ◽  
Yuan Gao ◽  
Xian Peng ◽  
...  
Keyword(s):  
Enterococcus Faecalis ◽  
Therapeutic Effect ◽  
Root Canal ◽  
Apical Periodontitis ◽  
Control Group ◽  
Root Canal Sealer ◽  
Root Canal Filling ◽  
First Time ◽  
Cone Beam Computer Tomography ◽  
Better Than

The infection of Enterococcus faecalis and its interacting microorganisms in the root canal could cause persistent apical periodontitis (AP). Antibacterial root canal sealer has favorable prospects to inhibit biofilms. The purpose of this study was to investigated the antibacterial effect of root canal sealer containing dimethylaminododecyl methacrylate (DMADDM) on persistent AP in beagle dogs for the first time. Persistent AP was established by a two-step infection with Enterococcus faecalis and multi-bacteria (Enterococcus faecalis, Lactobacillus acidophilus, Actinomycesnaeslundii, Streptococcus gordonii). Root canal sealer containing DMADDM (0%, 1.25%, 2.5%) was used to complete root canal filling. The volume of lesions and inflammatory grade in the apical area were evaluated by cone beam computer tomography (CBCT) and hematoxylin-eosin staining. Both Enterococcus-faecalis- and multi-bacteria-induced persistent AP caused severe apical destruction, and there were no significant differences in pathogenicity between them. DMADDM-modified sealer significantly reduced the volume of periapical lesion and inflammatory grade compared with the control group, among them, the therapeutic effect of the 2.5% group was better than the 1.25% group. In addition, E.faecalis-induced reinfection was more sensitive to the 2.5% group than multi-bacteria reinfection. This study shows that root canal sealer containing DMADDM had a remarkable therapeutic effect on persistent AP, especially on E. faecalis-induced reinfection.

scholarly journals CPC2 Reduction with Hipparcos and Proper Motions in The Southern Hemisphere

1998 ◽  
Vol 11 (1) ◽  
pp. 551-551
Author(s):  
N. Zacharias ◽  
M.I. Zacharias ◽  
C. de Vegt ◽  
C.A. Murray
Keyword(s):  
Southern Hemisphere ◽  
Systematic Errors ◽  
Reference Star ◽  
Proper Motions ◽  
Positional Accuracy ◽  
Star Catalog ◽  
Naval Observatory ◽  
Celestial Reference System ◽  
First Time ◽  
Better Than

The Second Cape Photographic Catalog (CPC2) contains 276,131 stars covering the entire Southern Hemisphere in a 4-fold overlap pattern. Its mean epoch is 1968, which makes it a key catalog for proper motions. A new reduction of the 5687 plates using on average 40 Hipparcos stars per plate has resulted in a vastly improved catalog with a positional accuracy of about 40 mas (median value) per coordinate, which comes very close to the measuring precision. In particular, for the first time systematic errors depending on magnitude and color can be solved unambiguously and have been removed from the catalog. In combination with the Tycho Catalogue (mean epoch 1991.25) and the upcoming U.S. Naval Observatory CCD Astrograph Catalog (UCAC) project proper motions better than 2 mas/yr can be obtained. This will lead to a vastly improved reference star catalog in the Southern Hemisphere for the final Astrographic Catalogue (AC) reductions, which will then provide propermotions for millions of stars when combined with new epoch data. These data then will allow an uncompromised reduction of the southern Schmidt surveys on the International Celestial Reference System (ICRS).

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