scholarly journals Design of CDTA and VDTA Based Frequency Agile Filters

2014 ◽  
Vol 2014 ◽  
pp. 1-15 ◽  
Author(s):  
Neeta Pandey ◽  
Aseem Sayal ◽  
Richa Choudhary ◽  
Rajeshwari Pandey
Keyword(s):  
Signal To Noise Ratio ◽  
Cmos Technology ◽  
Functional Verification ◽  
Model Parameters ◽  
Maximum Output ◽  
Passive Components ◽  
Transconductance Amplifier ◽  
Frequency Agile ◽  
Output Noise ◽  
Current Difference

This paper presents frequency agile filters based on current difference transconductance amplifier (CDTA) and voltage difference transconductance amplifier (VDTA). The proposed agile filter configurations employ grounded passive components and hence are suitable for integration. Extensive SPICE simulations using 0.25 μm TSMC CMOS technology model parameters are carried out for functional verification. The proposed configurations are compared in terms of performance parameters such as power dissipation, signal to noise ratio (SNR), and maximum output noise voltage.

TIME MARKER GENERATOR USING OPERATIONAL TRANSCONDUCTANE AMPLIFIER

2015 ◽  
Vol 76 (1) ◽  
Author(s):  
Avireni Srinivasulu ◽  
V. Tejaswini ◽  
T. Pitchaiah
Keyword(s):  
Sine Wave ◽  
Experimental Results ◽  
Model Parameters ◽  
Operational Transconductance Amplifier ◽  
Passive Components ◽  
Time Marker ◽  
Square Wave ◽  
Transconductance Amplifier ◽  
Technology Process ◽  
Wave Converter

This letter introduces time marker generator (TMG) using operational transconductance amplifier (OTA). It is composed of comparator (i.e. sine wave to square wave converter), integrator and clipper. The performance of the proposed circuit is examined using Cadence and the model parameters of a 180 nm technology process.  Later, the circuit was built with commercially available OTA (LM 13600), passive components used externally and tested at the outputs of comparator, integrator and clipper. Simulations and experimental results are shown that verify the proposed circuit of time marker generator.

scholarly journals Single CDTA-Based Current Mode All-Pass Filter and Its Applications

2011 ◽  
Vol 2011 ◽  
pp. 1-5 ◽  
Author(s):  
Neeta Pandey ◽  
Sajal K. Paul
Keyword(s):  
Input Impedance ◽  
Current Mode ◽  
Cmos Technology ◽  
Band Pass Filter ◽  
Output Impedance ◽  
Spice Simulation ◽  
Pass Filter ◽  
Transconductance Amplifier ◽  
Band Pass ◽  
Current Difference

This paper presents a single current difference transconductance amplifier (CDTA) based all-pass current mode filter. The proposed configuration makes use of a grounded capacitor which makes it suitable for IC implementation. Its input impedance is low and output impedance is high, hence suitable for cascading. The circuit does not use any matching constraint. The nonideality analysis of the circuit is also given. Two applications, namely, a quadrature oscillator and a highQband pass filter are developed with the proposed circuit. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.

scholarly journals Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA

2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
Neeta Pandey ◽  
Rajeshwari Pandey
Keyword(s):  
Current Mode ◽  
Cmos Technology ◽  
Spice Simulation ◽  
Full Wave ◽  
Transconductance Amplifier ◽  
Current Difference ◽  
A Current

This paper presents a current mode full-wave rectifier based on single modified Z copy current difference transconductance amplifier (MZC-CDTA) and two switches. The circuit is simple and is suitable for IC implementation. The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.

scholarly journals Compact Continuous Time Common-Mode Feedback Circuit for Low-Power, Area-Constrained Neural Recording Amplifiers

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 145
Author(s):  
Joon Young Kwak ◽  
Sung-Yun Park
Keyword(s):  
Low Power ◽  
Continuous Time ◽  
Cmos Technology ◽  
Neural Recording ◽  
Low Noise ◽  
Common Mode ◽  
Passive Components ◽  
Fully Differential ◽  
Transconductance Amplifier ◽  
Differential Difference Amplifier

A continuous-time common-mode feedback (CMFB) circuit for low-power, area-constrained neural recording amplifiers is proposed. The proposed CMFB circuit is compact; it can be realized by simply replacing passive components with transistors in a low-noise folded cascode operational transconductance amplifier (FC-OTA) that is one of the most widely adopted OTAs for neural recording amplifiers. The proposed CMFB also consumes no additional power, i.e., no separate CMFB amplifier is required, thus, it fits well to low-power, area-constrained multichannel neural recording amplifiers. The proposed CMFB is analyzed in the implementation of a fully differential AC-coupled neural recording amplifier and compared with that of an identical neural recording amplifier using a conventional differential difference amplifier-based CMFB in 0.18 μm CMOS technology post-layout simulations. The AC-coupled neural recording amplifier with the proposed CMFB occupies ~37% less area and consumes ~11% smaller power, providing 2.67× larger output common mode (CM) range without CM bandwidth sacrifice in the comparison.

scholarly journals Tunable Lossy and Lossless Grounded Inductors Using Minimum Active and Passive Components

2021 ◽  
Vol 11 (3) ◽  
pp. 171-190
Author(s):  
Tapas Kumar Paul ◽  
Suvajit Roy ◽  
Radha Raman Pal
Keyword(s):  
Power Dissipation ◽  
Maximum Output ◽  
Passive Components ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Transconductance Amplifier ◽  
Low Pass ◽  
Component Matching ◽  
Band Pass ◽  
Electronically Tunable

In this contribution, nine new Grounded Inductance Simulators (GISs) using a single Multiple-Output Current Controlled Current Conveyor Transconductance Amplifier (MO-CCCCTA) and one grounded capacitor are proposed. Among them, two are lossless types and seven are lossy types. The use of a single grounded capacitor makes the circuits suitable for fabrication. All the proposed circuits are electronically tunable through the bias currents of MO-CCCCTA. Furthermore, no component matching conditions are needed for realizing them. The designed circuits are verified through PSPICE simulator with ± 0.9 V power supply. The simulation results show that for all the proposed circuits: maximum operating frequencies are about 12 MHz, power dissipation is less than 0.784 mW, Total Harmonic Distortions (THDs) are under 8.09%, and maximum output voltage noise at 1 MHz frequency is 14.094 nV/√Hz. To exhibit the workability of the proposed circuits, they are used to design band-pass, low-pass filter, parallel RLC resonator, and parasitic inductance cancelator.

Copper Ulsi Interconnect Technology

1998 ◽  
Vol 514 ◽  
Author(s):  
D. Edelstein
Keyword(s):  
High Performance ◽  
Stress Testing ◽  
Cmos Technology ◽  
Functional Verification ◽  
Functional Modules ◽  
Mos Devices ◽  
Potential Problems ◽  
Cu Contamination ◽  
Interconnect Technology ◽  
Better Than

ABSTRACTRecently IBM announced the first implementation of full copper ULSI wiring in a CMOS technology, to be manufactured on its high-performance 0.22 um CMOS products this year. Features of this technology will be presented, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data will be presented fom all aspects of this testing, ranging from experiments designed to promote Cu contamination of the MOS devices, to temperature/humidity/bias stressing of assembled functional modules. The results in all areas are shown to be equal to or better than standards set by our current AI(Cu)/Wstud technology. This demonstrates that the potential problems associated with copper wiring that have long been discussed can be overcome.

scholarly journals Information gain from isotopic contrast variation in neutron reflectometry on protein–membrane complex structures

2020 ◽  
Vol 53 (3) ◽  
pp. 800-810
Author(s):  
Frank Heinrich ◽  
Paul A. Kienzle ◽  
David P. Hoogerheide ◽  
Mathias Lösche
Keyword(s):  
Experimental Design ◽  
Soft Matter ◽  
Lipid Membrane ◽  
Information Gain ◽  
Signal To Noise Ratio ◽  
Scattering Length ◽  
Model Parameters ◽  
Membrane Complex ◽  
Simple Model System ◽  
Molecular Components

A framework is applied to quantify information gain from neutron or X-ray reflectometry experiments [Treece, Kienzle, Hoogerheide, Majkrzak, Lösche & Heinrich (2019). J. Appl. Cryst. 52, 47–59], in an in-depth investigation into the design of scattering contrast in biological and soft-matter surface architectures. To focus the experimental design on regions of interest, the marginalization of the information gain with respect to a subset of model parameters describing the structure is implemented. Surface architectures of increasing complexity from a simple model system to a protein–lipid membrane complex are simulated. The information gain from virtual surface scattering experiments is quantified as a function of the scattering length density of molecular components of the architecture and the surrounding aqueous bulk solvent. It is concluded that the information gain is mostly determined by the local scattering contrast of a feature of interest with its immediate molecular environment, and experimental design should primarily focus on this region. The overall signal-to-noise ratio of the measured reflectivity modulates the information gain globally and is a second factor to be taken into consideration.

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
pp. 1-6
Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

scholarly journals Gm-Realization of Controlled-Gain Current Follower Transconductance Amplifier

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
Worapong Tangsrirat
Keyword(s):  
Current Mode ◽  
Cmos Technology ◽  
Current Transfer ◽  
Biquad Filter ◽  
Transconductance Amplifier ◽  
Current Follower ◽  
Dc Bias ◽  
Simulation Results ◽  
Supply Voltages ◽  
A Current

This paper describes the conception of the current follower transconductance amplifier (CFTA) with electronically and linearly current tunable. The newly modified element is realized based on the use of transconductance cells (Gms) as core circuits. The advantage of this element is that the current transfer ratios (iz/ipandix/iz) can be tuned electronically and linearly by adjusting external DC bias currents. The circuit is designed and analyzed in 0.35 μm TSMC CMOS technology. Simulation results for the circuit with ±1.25 V supply voltages show that it consumes only 0.43 mw quiescent power with 70 MHz bandwidth. As an application example, a current-mode KHN biquad filter is designed and simulated.

New Grounded and Floating Memristor-Less Meminductor Emulators Using VDTA and CDBA

2021 ◽  
pp. 2150283
Author(s):  
Nisha Yadav ◽  
Shireesh Kumar Rai ◽  
Rishikesh Pandey
Keyword(s):  
Adaptive Learning ◽  
Hysteresis Loops ◽  
Cmos Technology ◽  
Chaotic Oscillator ◽  
Simulation Tool ◽  
Analog Multiplier ◽  
Transconductance Amplifier ◽  
Simulation Results ◽  
Pinched Hysteresis

In this paper, new memristor-less meminductor emulators have been proposed using voltage differencing transconductance amplifier (VDTA), current differencing buffered amplifier (CDBA) and a grounded capacitor. The proposed decremental/incremental meminductor emulators have been realized in both grounded and floating types of configurations. In the proposed meminductor emulators, analog multiplier, memristor and passive resistors are not used which result in simpler configurations. The pinched hysteresis loops are maintained up to 2[Formula: see text]MHz for both decremental and incremental configurations of meminductor emulators. The behaviors of decremental and incremental meminductor emulators have been analyzed after applying input pulses. The obtained results verify the performances as decremental and incremental meminductor emulators. The simulation results have been obtained using Mentor Graphics Eldo simulation tool with 180[Formula: see text]nm CMOS technology parameters. To verify the performances of the proposed meminductor emulators, adaptive learning circuit and chaotic oscillator have been designed. The performances of the proposed meminductor emulators are compared with other meminductor emulators reported in the literature.

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