scholarly journals Study of Linearity and Power Consumption Requirements of CMOS Low Noise Amplifiers in Context of LTE Systems and Beyond

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Grzegorz Szczepkowski ◽  
Ronan Farrell
Keyword(s):  
Power Consumption ◽  
Antenna Arrays ◽  
Noise Figure ◽  
Low Noise ◽  
Base Stations ◽  
Small Cells ◽  
Handheld Devices ◽  
Low Noise Amplifiers ◽  
Budget Planning

This paper presents a study of linearity in wideband CMOS low noise amplifiers (LNA) and its relationship to power consumption in context of Long Term Evolution (LTE) systems and its future developments. Using proposed figure of merit (FoM) to compare 35 state-of-the-art LNA circuits published over the last decade, the paper explores a dependence between amplifier performance (i.e., combined linearity, noise figure, and gain) and power consumption. In order to satisfy stringent linearity specifications for LTE standard (and its likely successors), the paper predicts that LNA FoM increase in the range of +0.2 dB/mW is expected and will inevitably translate into a significant increase in power consumption—a critical budget planning aspect for handheld devices, active antenna arrays, and base stations operating in small cells.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

scholarly journals Technologies, Design, and Applications of Low-Noise Amplifiers at Millimetre-Wave: State-of-the-Art and Perspectives

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1222 ◽  
Author(s):  
Longhi ◽  
Pace ◽  
Colangeli ◽  
Ciccognani ◽  
Limiti
Keyword(s):  
Integrated Circuit ◽  
Noise Figure ◽  
State Of The Art ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Wave State ◽  
Millimetre Wave ◽  
Monolithic Microwave Integrated Circuit ◽  
V Band ◽  
And Performance

An overview of applicable technologies and design solutions for monolithic microwave integrated circuit (MMIC) low-noise amplifiers (LNAs) operating at millimeter-wave are provided in this paper. The review starts with a brief description of the targeted applications and corresponding systems. Advanced technologies are presented highlighting potentials and drawbacks related to the considered possibilities. Design techniques, applicable to different requirements, are presented and analyzed. An LNA operating at V-band (59–66 GHz) is designed and tested following the presented guidelines, demonstrating state-of-the-art results in terms of noise figure (average NF < 2 dB). A state-of-the-art table, reporting recent results available in open literature on this topic, is provided and examined, focusing on room temperature operation and performance in cryogenic environment. Finally, trends versus frequency and perspectives are outlined.

ON-CHIP INDUCTORS OPTIMIZATION FOR ULTRA WIDE BAND LOW NOISE AMPLIFIERS

2011 ◽  
Vol 20 (07) ◽  
pp. 1231-1242 ◽  
Author(s):  
J. DEL PINO ◽  
SUNIL L. KHEMCHANDANI ◽  
ROBERTO DÍAZ-ORTEGA ◽  
R. PULIDO ◽  
H. GARCÍA-VÁZQUEZ
Keyword(s):  
Quality Factor ◽  
Noise Figure ◽  
Impedance Matching ◽  
Broad Band ◽  
Wide Band ◽  
Design Guidelines ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Integrated Inductor ◽  
On Chip

In this work, the influence of the inductor quality factor in wide band low noise amplifiers has been studied. Electromagnetic simulations have been used to model the integrated inductor broad band response. The influence of the quality factor on LNA performance of the inductors that compound the impedance matching networks, inductive degeneration and broadband load has been studied, obtaining design guidelines for optimizing the amplifier gain flatness. Using this guidelines, an LNA with wideband input matching, shunt-peaking load, and an output buffer was designed. Using Austria Mikro Systems BiCMOS 0.35 m process, a prototype has been fabricated achieving the following measured specifications: maximum gain of 12.5 dB at 3.4 GHz with a -3 dB bandwidth of 1.7–5.3 GHz, noise figure from 4.3 to 5.2 dB, and unity gain at 9.4 GHz.

scholarly journals Metamodelling Techniques for the Optimal Design of Low-Noise Amplifiers

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 787
Author(s):  
Amel Garbaya ◽  
Mouna Kotti ◽  
Mourad Fakhfakh ◽  
Esteban Tlelo-Cuautle
Keyword(s):  
Particle Swarm Optimization ◽  
Optimal Design ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Scattering Parameters ◽  
Perfect Agreement ◽  
Swarm Optimization ◽  
The Third ◽  
Intercept Point

In this article we deal with the optimal sizing of low-noise amplifiers (LNAs) using newly proposed metamodeling techniques. The main objective is to construct metamodels of main performances of the LNAs (namely, the third intercept point (IIP3), the scattering parameters (Sij), and the noise figure (NF)) and use them inside an optimization kernel for maximizing the circuits’ performances. The kriging surrogate modelling technique is used for constructing these models. The particle swarm optimization (PSO) technique is considered as the optimization metaheuristic. Two CMOS amplifiers are considered: a UMTS LNA and a multistandard LNA. Obtained results show that, at the considered working frequencies, the first LNA exhibits at 2.14 GHz a noise figure of 1.30 dB, an S21 of 16.01 dB, an S11 of −12.60 dB, and an IIP3 of 8.30 dBm. At 2 GHz, the second LNA has a noise figure of 1.24 dB, an S21 of 17.16 dB, an S11 of −13.74 dB, and an IIP3 of 4.30 dBm. Comparisons between results obtained using the constructed models and those of the simulation are presented to show the perfect agreement between them.

Noise figure measurement of three-port differential low-noise amplifiers

2012 ◽  
Vol 48 (10) ◽  
pp. 578 ◽  
Author(s):  
D.S. Prinsloo ◽  
P. Meyer
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers

scholarly journals Bandwidth Analysis of a Broadband Amplifier with Two-Stage Matching System Using the Smith Chart

2021 ◽  
Vol 24 (3) ◽  
pp. 53-60
Author(s):  
A.A. Sherstneva
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Matching Problem ◽  
Two Stage ◽  
Analysis And Design ◽  
Design Variables ◽  
Stage Matching ◽  
Smith Chart

This paper describes a novel trace structure for the analysis and design of two-stage Broadband Frequency Low Noise Amplifiers based on standard Smith chart procedures and program algorithm realization. The method allows to put the transistor's S-parameters and details of the source and load networks and to interactively explore the effects of these quantities on design variables such as gain, noise figure and stability. It also facilitates the design of two-element matching networks to transform the source and load impedances to optimum values to achieve the desired gain and noise performance. The extended Smith chart concept is proposed to enable the advanced graphical interpretation of devices containing complex properties. This methodology is based on the Smith chart concept, and makes it easy to deal with devices containing signal sources, nonlinearity, very high Q factors and negative resistances. The concept of explaining the use of the Smith chart in combination with using modern tools as MATLAB scripts is exemplified in graphical forms. Phyton-based program contains the algorithm for parameters calculation. It explains the procedure that must be used to solve the two-stage impedance-matching problem. The point of this proposal is using of Smith chart plane for the graphical processing for its application to oscillator analysis. To demonstrate the effective usage of this methodology an interpretation and analysis of the oscillator, especially in terms of gain, noise and stability, are provided. The practical relevance concludes results of multistage design using impedance matching LC networks for the intersection level. The values of the parameters of the integrated microcircuit confirm the possibility of using the calculation methodology considered in the paper. The proposed solution is validated with extensive RF measurements at 3.5 GHz and is benchmarked against several frequency ranges for noise, stability and gain values. The methodology shown in the paper can be used in the development and design of modern microwave amplifiers, as well as for research and analysis of the efficiency of existing devices.

Design of High Performance Low-Noise Amplifier Circuit Based on Complementary Metal Oxide Semiconductor Technology

2021 ◽  
Vol 16 (4) ◽  
pp. 559-564
Author(s):  
Chao Huang ◽  
Wan-Jun Yin
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Input Device ◽  
Output Stage ◽  
Noise Amplifier ◽  
5 Ghz

This paper designs a body-biased (BB) differential cascode low-noise amplifier (LNA) with current bias (CR) and capacitor cross-coupling (CCC) technology that meets the bandwidth requirements of 5 GHz wireless applications. In the design, the CCC technology in the differential cascode topology is used to effectively suppress the common mode noise, thereby improving the noise figure. The series resonant network eliminates parasitic capacitance at the input and output ends, thereby improving the power transmission efficiency. The CR technology formed by the intermediate capacitor shares the DC current input to the output device, thereby increasing the gain. This paper uses BB technology in the design to lower the threshold of the cascode device and improve the transconductance, which further improves the gain and reduces the power consumption. The CCC technology used in the paper improves linearity by eliminating the non-linear components present in the input device, which will not interfere with the transconductance of the output stage. This article has obtained excellent performance parameters including gain, noise figure (NF) and linearity without affecting the power consumption, integration and cost of the proposed design.

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