scholarly journals A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise

2018 ◽  
Vol 2018 ◽  
pp. 1-16
Author(s):  
Candy Goyal ◽  
Jagpal Singh Ubhi ◽  
Balwinder Raj
Keyword(s):  
Signal To Noise Ratio ◽  
Average Power ◽  
Full Adder ◽  
Leakage Power ◽  
Reduction Technique ◽  
Signal To Noise ◽  
Design Metrics ◽  
Ground Bounce ◽  
Power Delay Product ◽  
Pmos Transistor

In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.

Approximate Full Adders for Energy Efficient Image Processing Applications

2021 ◽  
pp. 2150235
Author(s):  
M. C. Parameshwara
Keyword(s):  
Energy Efficient ◽  
State Of The Art ◽  
Signal To Noise Ratio ◽  
Full Adder ◽  
Signal To Noise ◽  
Design Metrics ◽  
Standard Cell Library ◽  
Cell Library ◽  
Fair Comparison ◽  
Power Delay Product

This paper proposes six novel approximate 1-bit full adders (AFAs) for inexact computing. The six novel AFAs namely AFA1, AFA2, AFA3, AFA4, AFA5, and AFA6 are derived from state-of-the-art exact 1-bit full adder (EFA) architectures. The performance of these AFAs is compared with reported AFAs (RAAs) in terms of design metrics (DMs) and peak-signal-to-noise-ratio (PSNR). The DMs under consideration are power, delay, power-delay-product (PDP), energy-delay-product (EDP), and area. For a fair comparison, the EFAs and proposed AFAs along with RAAs are described in Verilog, simulated, and synthesized using Cadences’ RC tool, using generic 180 nm standard cell library. The unconstrained synthesis results show that: among all the proposed AFAs, the AFA1 and AFA2 are found to be energy-efficient adders with high PSNR. The AFA1 has a total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB. And the AFA2 has the total [Formula: see text][Formula: see text][Formula: see text]W, [Formula: see text][Formula: see text]ps, [Formula: see text][Formula: see text]fJ, [Formula: see text][Formula: see text]Js, [Formula: see text][Formula: see text][Formula: see text]m2, and [Formula: see text][Formula: see text]dB.

Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications

2016 ◽  
Vol 26 (01) ◽  
pp. 1750014 ◽  
Author(s):  
M. C. Parameshwara ◽  
H. C. Srinivasaiah
Keyword(s):  
Supply Voltage ◽  
Average Power ◽  
Full Adder ◽  
Signal Frequency ◽  
Design Metrics ◽  
Input Signal Frequency ◽  
Implementation Approach ◽  
Pass Transistor ◽  
Power Delay Product ◽  
Generic Process

A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118[Formula: see text][Formula: see text]W, with a delay of 606 ps, with an area of 33.1[Formula: see text][Formula: see text]m2, resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage [Formula: see text][Formula: see text]V, input signal frequency [Formula: see text][Formula: see text]MHz is used. This 1-bit FA is designed and implemented using Cadences' 90[Formula: see text]nm “generic-process-design-kit” (GPDK).

scholarly journals Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology

2019 ◽  
Vol 14 (2) ◽  
pp. 912
Author(s):  
Woo Wei Kai ◽  
Nabihah Ahmad ◽  
Mohamad Hairol Jabbar
Keyword(s):  
Low Power ◽  
Average Power ◽  
Full Adder ◽  
Oxide Thickness ◽  
Low Complexity ◽  
Operating Voltage ◽  
Short Channel ◽  
Static Power ◽  
Subthreshold Leakage ◽  
Power Delay Product

In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of  supply. The result showed the reduction of VBB technique in term of peak power,  and average power,   compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.

Study on Fast Algorithm for SNR and Method for Threshold Confirmation

2013 ◽  
Vol 427-429 ◽  
pp. 1718-1722
Author(s):  
Lin Sun ◽  
Ran Wei ◽  
Fu Ting Bao ◽  
Xian Zhang Tian
Keyword(s):  
Power Spectrum ◽  
Fast Algorithm ◽  
Human Gene ◽  
Signal To Noise Ratio ◽  
Average Power ◽  
Threshold Value ◽  
Computational Experiments ◽  
Rigorous Derivation ◽  
Signal To Noise ◽  
Average Power Spectrum

To reduce the amount of computing resources, a fast algorithm of the average power spectrum and signal-to-noise ratio was presented based on rigorous derivation of the formula. Also, it proved the rule gained from computational experiments. Besides, a method called fitting-optimization to determine the classification threshold value was proposed. It improves the accuracy by about 7% for human gene.

A low-PDAP and high-PSNR approximate 4:2 compressor cell in CNFET technology

Circuit World ◽  
2019 ◽  
Vol 45 (3) ◽  
pp. 156-168 ◽  
Author(s):  
Yavar Safaei Mehrabani ◽  
Mehdi Bagherizadeh ◽  
Mohammad Hossein Shafiabadi ◽  
Abolghasem Ghasempour
Keyword(s):  
Image Processing ◽  
Design Methodology ◽  
Figure Of Merit ◽  
Signal To Noise Ratio ◽  
Monte Carlo Analysis ◽  
The Other ◽  
Threshold Logic ◽  
Signal To Noise ◽  
Content Type ◽  
Power Delay Product

Purpose This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs). Design/methodology/approach To design this cell, the capacitive threshold logic (CTL) has been used. Findings To evaluate the proposed cell, comprehensive simulations are carried out at two levels of the circuit and image processing. At the circuit level, the HSPICE software has been used and the power consumption, delay, and power-delay product are calculated. Also, the power-delaytransistor count product (PDAP) is used to make a compromise between all metrics. On the other hand, the Monte Carlo analysis has been used to scrutinize the robustness of the proposed cell against the variations in the manufacturing process. The results of simulations at this level of abstraction indicate the superiority of the proposed cell to other circuits. At the application level, the MATLAB software is also used to evaluate the peak signal-to-noise ratio (PSNR) figure of merit. At this level, the two primary images are multiplied by a multiplier circuit consisting of 4:2 compressors. The results of this simulation also show the superiority of the proposed cell to others. Originality/value This cell significantly reduces the number of transistors and only consists of NOT gates.

scholarly journals Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
‘Aqilah binti Abdul Tahrim ◽  
Huei Chaeng Chin ◽  
Cheng Siong Lim ◽  
Michael Loong Peng Tan
Keyword(s):  
High Speed ◽  
Average Power ◽  
Full Adder ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Subthreshold Region ◽  
And Performance ◽  
Power Delay Product ◽  
20 Nm

The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

Design and Simulation of OFDM System Based on Matlab

2014 ◽  
Vol 635-637 ◽  
pp. 1081-1085
Author(s):  
Xin Xin Sha ◽  
Jian Zhou ◽  
Yuan Xue Song
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Channel Coding ◽  
Signal To Noise Ratio ◽  
Average Power ◽  
System Structure ◽  
Power Ratio ◽  
Basic System ◽  
Ofdm System ◽  
Signal To Noise

OFDM is a key modulation and multiplexing technique. The basic system structure of OFDM is introduced firstly. This paper chose appropriate implementation schemes for channel coding, PAPR(Peak To Average Power Ratio) reducing and synchronization of the OFDM system based on the minimum BER(Bit Error Rate). Finally, the paper realized the simulation and got the BER in different SNR(Signal To Noise Ratio) in the matlab environment .

A New Keeper Domino Logic Based Full Adder for High Speed Arithmetic Circuits

2020 ◽  
Vol 12 ◽  
Author(s):  
Deepika Bansal ◽  
Bal Chand Nagar ◽  
Ajay Kumar ◽  
Brahamdeo Prasad Singh
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
High Efficiency ◽  
Dynamic Logic ◽  
Full Adder ◽  
Leakage Power ◽  
Low Leakage ◽  
Dynamic Circuits ◽  
Power Delay Product ◽  
Domino Circuits

Objective: A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET. Method: As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature. Result: The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies. Conclusion: A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50% respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.

scholarly journals Low Voltage Full Swing FinFET Hybrid Full Adder

2019 ◽  
Vol 8 (2) ◽  
pp. 4253-4263
Keyword(s):  
Power Dissipation ◽  
Low Voltage ◽  
Average Power ◽  
Full Adder ◽  
Voltage Range ◽  
Lower Power ◽  
Low Power Dissipation ◽  
Power Delay Product ◽  
Full Swing ◽  
Cmos Implementation

In this research paper, CMOS and FinFET based hybrid Full Adders operating at low voltages with low power dissipation are proposed. The proposed CMOS based circuit is compared with few existing hybrid full adders in terms of average power dissipation and power-delay-product (PDP). The designed CMOS based hybrid adder achieves lower power dissipation and low PDP compared to other hybrid adders over a voltage range of 0.6V to 1V. The proposed CMOS implementation of hybrid full adder fails at 0.5V to produce full swing output. To solve this full swing problem, the proposed hybrid full adder is implemented using FinFETs which produce full output voltage, lower power and low PDP comparing with CMOS implementation. The circuits are designed with HSPICE tool in 32nm predictive technology model (PTM).

Design of Imprecise Multipliers by Using Approximate Technique for Error Resilient Applications

2020 ◽  
pp. 2150114
Author(s):  
M. Priyadharshni ◽  
S. Kumaravel
Keyword(s):  
Signal To Noise Ratio ◽  
Tree Structure ◽  
Approximate Computing ◽  
Least Significant Bit ◽  
Computational Accuracy ◽  
Verilog Hdl ◽  
Signal To Noise ◽  
Error Resilient ◽  
Noise Ratio ◽  
Power Delay Product

Approximate computing is the perfect way for error resilient applications with progress in speed and power but tradeoff with computational accuracy. In this paper, Imprecise Multipliers (IMs) are realized by segregating the partial products into two segments. The most significant bit (MSB) segment is accumulated as per Dadda tree structure and the least significant bit (LSB) segment is accumulated by approximate technique. The proposed Imprecise Multipliers, namely [Formula: see text] and [Formula: see text] are realized using Verilog HDL and simulated using TSMC 65[Formula: see text]nm process. For sake of comparison, the proposed multipliers [Formula: see text] and [Formula: see text] are compared with existing approximate multipliers. From the reported results, it may be noted that [Formula: see text] performs better in terms of area–delay product, power–delay product. While [Formula: see text] achieves a higher peak signal-to-noise ratio (PSNR) among all the multipliers existing in the literature.

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