Advanced SiP Packaging Technologies of IPD for Mobile Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 1-20
Author(s):  
Geun Sik Kim ◽  
Kai Liu ◽  
Flynn Carson ◽  
Seung Wook Yoon ◽  
Meenakshi Padmanathan
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Autonomous Systems ◽  
System Level ◽  
Design And Technology ◽  
Wafer Level ◽  
Future Technology ◽  
Rf Transceivers ◽  
And Performance ◽  
3D Stacking

IPD technology was originally developed as a way to replace bulky discrete passive components, but it¡¯s now gaining popularity in ESD/EMI protection applications, as well as in RF, high-brightness LED silicon sub-mounts, and digital and mixed-signal devices. Already well known as a key enabler of system-in-packages (SiPs), IPDs enable the assembly of increasingly complete and autonomous systems with the integration of diverse electronic functions such as sensors, RF transceivers, MEMS, power amplifiers, power management units, and digital processors. The application area for IPD will continue to evolve, especially as new packaging technology, such as flipchip, 3D stacking, wafer level packaging become available to provide vertical interconnections within the IPD. New applications like silicon interposers will become increasingly significant to the market. Currently the IPD market is being driven primarily by RF or wireless packages and applications including, but not limited to, cell phones, WiFi, GPS, WiMAX, and WiBro. In particular, applications and products in the emerging RF CMOS market that require a low cost, smaller size, and high performance are driving demand. In order to get right products in size and performance, packaging design and technology should be considered in device integration and implemented together in IPD designs. In addition, a comprehensive understanding of electrical and mechanical properties in component and system level design is important. This paper will highlight some of the recent advancements in SiP technology for IPD and integration as well as what is developed to address future technology requirements in IPD SiP solutions. The advantage and applications of SiP solution for IPD will be presented with several examples of IPD products. The design, assembly and packaging challenges and performance characteristics will be also discussed.

RF-MEMS Components and Networks for High-Performance Reconfigurable Telecommunication and Wireless Systems

2012 ◽  
Vol 81 ◽  
pp. 65-74 ◽  
Author(s):  
Jacopo Iannacci ◽  
Giuseppe Resta ◽  
Paola Farinelli ◽  
Roberto Sorrentino
Keyword(s):  
High Performance ◽  
Microelectromechanical Systems ◽  
Rf Mems ◽  
Low Cost ◽  
Impedance Matching ◽  
Phase Shifters ◽  
Rf Systems ◽  
Mems Technology ◽  
And Performance ◽  
Rf Performance

MEMS (MicroElectroMechanical-Systems) technology applied to the field of Radio Frequency systems (i.e. RF-MEMS) has emerged in the last 10-15 years as a valuable and viable solution to manufacture low-cost and very high-performance passive components, like variable capacitors, inductors and micro-relays, as well as complex networks, like tunable filters, reconfigurable impedance matching networks and phase shifters, and so on. The availability of such components and their integration within RF systems (e.g. radio transceivers, radars, satellites, etc.) enables boosting the characteristics and performance of telecommunication systems, addressing for instance a significant increase of their reconfigurability. The benefits resulting from the employment of RF-MEMS technology are paramount, being some of them the reduction of hardware redundancy and power consumption, along with the operability of the same RF system according to multiple standards. After framing more in detail the whole context of RF MEMS technology, this paper will provide a brief introduction on a typical RF-MEMS technology platform. Subsequently, some relevant examples of lumped RF MEMS passive elements and complex reconfigurable networks will be reported along with their measured RF performance and characteristics.

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-19
Author(s):  
Raquel Pinto ◽  
André Cardoso ◽  
Sara Ribeiro ◽  
Carlos Brandão ◽  
João Gaspar ◽  
...  
Keyword(s):  
Structural Material ◽  
High Performance ◽  
Microelectromechanical Systems ◽  
Low Cost ◽  
Process Conditions ◽  
Processing Temperature ◽  
Wafer Level ◽  
Fast Growing ◽  
Wide Range ◽  
Different Types

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.

FPGA-Based Test Equipment for System-Level MEMS Switch Series

2015 ◽  
Vol 645-646 ◽  
pp. 572-576
Author(s):  
Peng Liu ◽  
Wen Zhong Lou ◽  
Yu Fei Lu ◽  
Xin Yu Feng
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Original Data ◽  
Test Equipment ◽  
System Level ◽  
Mems Switch ◽  
Real Time Analysis ◽  
Embedded Algorithms ◽  
Equipment System

A high-performance, low-cost test equipment system for characterization of MEMS switch is to be proposed in this paper, and the purpose is set to master the fundament of the embedded algorithms of the wafer and system production testing. The team has implemented the real-time analysis for MEMS switch, proving the feasibility of the design, based on the original data collected during the dedicated tests, applying the microsystem hardware designed and assembled by the research team, as well as the embedded software. At the end, the framework of the system platform in the future is described.

A 3‐dB Quadrature WLP Coupler for 60 GHz Applications

2012 ◽  
Vol 1427 ◽  
Author(s):  
Hamid Kiumarsi ◽  
Hiroyuki Ito ◽  
Noboru Ishihara ◽  
Kenichi Okada ◽  
Yusuke Uemichi ◽  
...  
Keyword(s):  
Insertion Loss ◽  
High Performance ◽  
Low Cost ◽  
Phase Error ◽  
Superior Performance ◽  
60 Ghz ◽  
Wafer Level ◽  
Chip Area ◽  
Wafer Level Packaging ◽  
Coupled Lines

ABSTRACTA 60 GHz tandem coupler using offset broadside coupled lines is proposed in a WLP (Wafer Level Packaging) technology. The fabricated coupler has a core chip area of 750 μm × 385 μm (0.288 mm2). The measured results show an insertion loss of 0.44 dB, an amplitude imbalance of 0.03 dB and a phase difference of 87.6° at 60 GHz. Also the measurement shows an insertion loss of less than 0.67 dB, an amplitude imbalance of less than 0.31 dB, a phase error of less than 3.7°, an isolation of more than 29.7 dB and a return loss of more than 27.9 dB at the input ant coupled ports and more than 14.3 dB at the direct and isolated ports over the frequency band of 57-66 GHz, covering 60 GHz band both in Japan and US. To the best of our knowledge the proposed coupler achieves the lowest ever reported insertion loss and amplitude imbalance for a 3-dB coupler on a silicon substrate. With its superior performance and lower cost compared to the CMOS counterparts, the proposed coupler is a suitable candidate for low-cost high-performance millimeter-wave systems.

scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
Low Cost ◽  
Three Dimensional ◽  
System Level ◽  
Process Conditions ◽  
Wafer Level ◽  
3D Integration ◽  
Bonding Pressure ◽  
Curing Conditions ◽  
Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect

2002 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Optimization Technique ◽  
Cost Effective ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Good Reliability ◽  
Mechanical Compliance

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.

scholarly journals Properties of Foamed Lightweight High-Performance Phosphogypsum-Based Ternary System Binder

2020 ◽  
Vol 10 (18) ◽  
pp. 6222 ◽  
Author(s):  
Girts Bumanis ◽  
Jelizaveta Zorica ◽  
Diana Bajare
Keyword(s):  
Ternary System ◽  
High Performance ◽  
Raw Materials ◽  
Low Cost ◽  
Construction Materials ◽  
Mineralogical Composition ◽  
Point Of View ◽  
Raw Material ◽  
Total Energy Consumption ◽  
And Performance

The potential of phosphogypsum (PG) as secondary raw material in construction industry is high if compared to other raw materials from the point of view of availability, total energy consumption, and CO2 emissions created during material processing. This work investigates a green hydraulic ternary system binder based on waste phosphogypsum (PG) for the development of sustainable high-performance construction materials. Moreover, a simple, reproducible, and low-cost manufacture is followed by reaching PG utilization up to 50 wt.% of the binder. Commercial gypsum plaster was used for comparison. High-performance binder was obtained and on a basis of it foamed lightweight material was developed. Low water-binder ratio mixture compositions were prepared. Binder paste, mortar, and foamed binder were used for sample preparation. Chemical, mineralogical composition and performance of the binder were evaluated. Results indicate that the used waste may be successfully employed to produce high-performance binder pastes and even mortars with a compression strength up to 90 MPa. With the use of foaming agent, lightweight (370–700 kg/m3) foam concrete was produced with a thermal conductivity from 0.086 to 0.153 W/mK. Water tightness (softening coefficient) of such foamed material was 0.5–0.64. Proposed approach represents a viable solution to reduce the environmental footprint associated with waste disposal.

SiP(System in Package) Solutions with Wafer Level Packaging Technology

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002226-002253 ◽  
Author(s):  
In Soo Kang ◽  
Jong Heon (Jay) Kim
Keyword(s):  
Embedded System ◽  
High Performance ◽  
Low Cost ◽  
Wafer Level ◽  
Molding Compound ◽  
Wafer Level Packaging ◽  
Ic Packaging ◽  
Chip Size ◽  
Bonding Technology ◽  
Small Form Factor

In mobile application, the WLP technology has been developing to make whole package size almost same as chip size. However, the I/O per chip unit area has increased so that it gets difficult to realize ideal pad pitch for better reliability. Recently, to achieve the thin and small size, high performance and low cost semiconductor package, Embedding Die and Fanout Technologies have been suggested and developed based on wafer level processing. In this work, as a solution of system in package, wafer level embedded package and fanout technology will be reviewed. Firstly, Wafer level embedded System in Package (WL-eSiP) which has daughter chip (small chip) embedded inside mother chip (bigger chip) without any special substrate has been suggested and developed. To realize wafer level embedded system in package (WL-eSiP), wafer level based new processes like wafer level molding for underfilling and encapsulation by molding compound without any special substrate have been applied and developed, including high aspect ratio Cu bumping, mold thinning and chip-to-wafer flipchip bonding. Secondly, Fan-out Package is considered as alternative package structure which means merged package structure of WLCSP (wafer level chip size package) and PCB process. We can make IC packaging widen area for SIP(System in Package) or 3D package. In addition, TSV and IPD are key enabling technology to meet market demands because TSV interconnection can provide wider bandwidth and high transmission speed due to vertical one compared to wire bonding technology and IPD can provide higher performance, more area saving to be assembled and small form factor compared to discrete passive components.

Microfabrication and Packaging Process for a Single-Chip Position, Navigation, and Timing System

2017 ◽  
Vol 2017 (1) ◽  
pp. 000208-000214 ◽  
Author(s):  
Junjun Huan ◽  
Vamsy P. Chodavarapu ◽  
George Xereas ◽  
Charles Allan
Keyword(s):  
Inertial Sensors ◽  
Low Cost ◽  
Autonomous Systems ◽  
Pressure Sensors ◽  
Single Crystal Silicon ◽  
High Volume ◽  
Leak Rate ◽  
Single Chip ◽  
Wafer Level ◽  
Crystal Silicon

Abstract The Global Positioning System (GPS) is the primary means of Positioning, Navigation, and Timing (PNT) for most civilian and military systems and applications. The rapid growth in autonomous systems has created a widespread interest in self-contained Inertial Navigation System (INS) for precise navigation and guidance in the absence of GPS. The microscale PNT systems need both specialized and low cost fabrication technologies to cost effectively bring these technologies to market. We describe an ultra-clean (low leak rate) wafer-level vacuum encapsulation microfabrication process of Micro-Electro-Mechanical Systems (MEMS) based sensors and devices. Using this process we have fabricated inertial sensors, frequency reference resonators, and pressure sensors. In addition to providing excellent resistance to shock and vibration, this combined microfabrication and packaging method would allow the use of high volume low cost plastic packaging at the device level. The microfabrication process is an 8” wafer process based on high aspect ratio bulk micromachining of a 30 μm thick single-crystal silicon device layer that is vacuum encapsulated at 10 mTorr between two silicon wafers with the demonstrated leak rate of only 6.5 × 10−18 atm cm3/s.

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