Study on ZrO2 Deposited Directly on Si as an Alternative Gate Dielectric Material

1999 ◽  
Vol 606 ◽  
Author(s):  
Wen-Jie Qi ◽  
Renee Nieh ◽  
Byoung Hun Lee ◽  
Youngjoo Jeon ◽  
Laegu Kang ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Dielectric Material ◽  
Oxide Thickness ◽  
Amorphous Structure ◽  
Flat Band ◽  
Equivalent Oxide Thickness ◽  
Low Leakage ◽  
Quantum Mechanical Effects

AbstractReactive-magnetron-sputtered ZrO2 thin film has been deposited on Si directly for gate dielectric application. Both structural and electrical properties of the ZrO2 film have been investigated. An amorphous structure for 30Å ZrO2 and a semi-amorphous structure for 200Å ZrO2 have been revealed. The sputtered film shows a good stoichiometry and a good structural stability of ZrO2 based on the X-ray photoelectron spectroscopy and Rutherford backscattering spectroscopy data. Thin equivalent oxide thickness of about 11.5Å was obtained without the consideration of quantum mechanical effects. A low leakage of less than 10−2 A/cm2 at ±1V relative to the flat band voltage was obtained for this 11.5Å equivalent oxide thickness Pt/ZrO2/Si structure. High effective dielectric breakdown and superior reliability properties have been demonstrated for ZrO2 gate dielectric.

Strategies for CMOS Low Equivalent Oxide Thickness Achievement with High-κ Oxides Grown on Si(001) by MBE

2008 ◽  
Vol 1073 ◽  
Author(s):  
Loic Becerra ◽  
Clément Merckling ◽  
Nicolas Baboux ◽  
Mario El-Kazzi ◽  
Guillaume Saint-Girons ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Molecular Beam ◽  
Oxide Thickness ◽  
Flat Band ◽  
Equivalent Oxide Thickness ◽  
Electrical Measurements ◽  
X Ray ◽  
High K ◽  
Density Of Interface States ◽  
Post Deposition

ABSTRACTAmorphous LaAlO3 high-k oxide was grown in a molecular beam epitaxy reactor on p-Si(001) using a thin γ-Al2O3 epitaxied buffer layer. Interfaces were free of SiO2 or silicates and remained abrupt despite the high temperature used for annealing, as X-ray photoelectron spectroscopy showed. Electrical measurements performed on as-deposited samples revealed a dielectric constant value close to that of the bulk, small equivalent oxide thickness and low density of interface states. But some negative charges were present, leading to a flat band voltage shift. Post deposition annealing with forming gas can correct this effect.

Single Wafer CVD of Silicon Nitride for Cmos Gate Applications

1999 ◽  
Vol 567 ◽  
Author(s):  
C. Pomarede ◽  
C. Werkhoven ◽  
J. Weidmann ◽  
T. Bergman ◽  
A. Gschwandtner ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Oxide Thickness ◽  
Equivalent Oxide Thickness ◽  
Silicon Nitride Films ◽  
Excellent Growth ◽  
Gate Dielectric Material ◽  
Cluster Tool

ABSTRACTThe MESC/CTMC compatible, Advance 2500 cluster tool made by ASM is evaluated for the manufacturing of CMOS gate stack structures based on CVD silicon nitride rather than thermally grown silicon oxide as the gate dielectric material, and polysilicon as the gate electrode material. With two different CVD chemistries excellent growth characteristics and thickness uniformity control of the silicon nitride is demonstrated. Electrical assessment reveals lower leakage current as compared to silicon oxide and minimal hysteresis in C-V curves, even for gates stacks that have an equivalent oxide thickness below 1.5nm. The best properties are for silicon nitride films that also have a low H2 content.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Nitrogen (N2) Implantation to Suppress Growth of Interfacial Oxide in Mocvd Bst and Sputtered Bst Films

1999 ◽  
Vol 567 ◽  
Author(s):  
Renee Nieh ◽  
Wen-Jie Qi ◽  
Yongjoo Jeon ◽  
Byoung Hun Lee ◽  
Aaron Lucas ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Nitrogen Concentration ◽  
Chemical Vapor ◽  
Future Generation ◽  
Oxide Thickness ◽  
Layer Growth ◽  
X Ray ◽  
Bst Films

ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate dielectric in future generation devices. The biggest obstacle to scaling the equivalent oxide thickness (EOT) of BST is an interfacial layer, SixOy, which forms between BST and Si. Nitrogen (N2) implantation into the Si substrate has been proposed to reduce the growth of this interfacial layer. In this study, capacitors (Pt/BST/Si) were fabricated by depositing thin BST films (50Å) onto N2 implanted Si in order to evaluate the effects of implant dose and annealing conditions on EOT. It was found that N2 implantation reduced the EOT of RF magnetron sputtered and Metal Oxide Chemical Vapor Deposition (MOCVD) BST films by ∼20% and ∼33%, respectively. For sputtered BST, an implant dose of 1×1014cm−;2 provided sufficient nitrogen concentration without residual implant damage after annealing. X-ray photoelectron spectroscopy data confirmed that the reduction in EOT is due to a reduction in the interfacial layer growth. X-ray diffraction spectra revealed typical polycrystalline structure with (111) and (200) preferential orientations for both films. Leakage for these 50Å BST films is on the order of 10−8 to 10−5 A/cm2—lower than oxynitrides with comparable EOTs.

Effect of Systematic Changes of Ti and Hf Si-oxynitride Alloys by Nitrogen Incorporation as a Bond Constraint on Electrical and Material Properties

2007 ◽  
Vol 996 ◽  
Author(s):  
Sanghyun Lee ◽  
Gerry Lucovsky ◽  
L. B. Fleming ◽  
Jan Luning
Keyword(s):  
Photoelectron Spectroscopy ◽  
Oxide Thickness ◽  
Ternary Alloys ◽  
Flat Band ◽  
Compositional Dependence ◽  
X Ray ◽  
State Splitting ◽  
Current Voltage ◽  
Current Voltage Characteristics ◽  
X Ray Absorption

AbstractWe have investigated the effect of Si3N4 content in (Ti(Hf)O2)x(Si3N4)y(SiO2)1-x-y pseudo-ternary alloys by tracking systematic changes of electrical properties, including electrically active defects. Results from Soft x-ray photoelectron spectroscopy (SXPS) studies indicate no detectable hole traps for Ti/Hf Si oxynitrides with Si3N4 content >35%; these alloys have equal concentrations of Ti(Hf)O2 and SiO2, ~30-32%, and additionally are stable for annealing in Ar ambients to temperatures of 1100°C. Derivative near edge x-ray absorption spectroscopy (NEXAS) comparisons for the O K1 edges of TiO2 and optimized Ti Si oxynitride alloys provides a significantly reduced average crystal field d-state splitting from 1.9 to 1.6eV, as well as decreased electron trapping, and is correlated with a four-fold coordination of Ti in the Ti Si oxynitride alloys. The flat band voltage shift with varying frequency from 10 kHz to 1MHz in these alloys is less than 12 mV and the compositional dependence of current-voltage characteristics on Si3N4 composition results in the lowest leakage current at a Si3N4 content of ~40 % with the smallest equivalent oxide thickness (EOT) as well. Based on these studies, Transition Metal (TM) Si oxynitride alloys are anticipated to yield EOT <1 nm for scaled CMOS devises.

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