H∞ Control law for line of sight stabilization in two-axis gimbal system

2020 ◽  
pp. 107754632097454
Author(s):  
M. Ashok Kumar ◽  
S. Kanthalakshmi
Keyword(s):  
Digital Signal Processor ◽  
Controller Design ◽  
Mathematical Formulation ◽  
Digital Signal ◽  
Line Of Sight ◽  
Experimental Frequency ◽  
Modeling Uncertainties ◽  
Air Vehicle ◽  
Sensitivity Problem ◽  
Air Vehicles

A two-axis gimbaled stabilization system in air vehicles must stabilize the line of sight of the payload toward a target against the external motion induced by air vehicle maneuvering and aerodynamic forces. The target tracking and pointing performances of the air vehicles are largely affected by air vehicle motion decoupling capability. In this work, the [Formula: see text] controller design is carried out for a two-axis gimbal system. The plant model is generated using experimental frequency response data and mathematical formulation of the system. The mixed sensitivity problem is posed and weighting functions are selected so that they not only fulfill all the design goals but also accommodate the modeling uncertainties. The stabilization loop is designed and implemented in digital signal processor-based hardware for only one axis (in azimuth).

scholarly journals Controller Design and Preliminary Testing of a Powered Below-Knee Prosthetic Device

2012 ◽  
Author(s):  
Jinming Sun ◽  
Philip A. Voglewede
Keyword(s):  
Digital Signal Processor ◽  
Controller Design ◽  
Digital Signal ◽  
Power Input ◽  
Dc Motor ◽  
Bench Test ◽  
Area Network ◽  
Level Control ◽  
Lower Limb Prosthesis ◽  
Dsp Control

A powered lower limb prosthesis, which consists of a four bar mechanism, a torsional spring and a brushed DC motor, was previously designed and fabricated. To regulate the motor power input, a two level controller was proposed and built. The control algorithm includes a higher level finite state controller and lower level PID controllers. A digital signal processor (DSP) control board and MATLAB Simulink are used to realize the higher level control and a DC motor controller is used to realize the lower level PID control. Controller Area Network (CAN) communication was used to communicate between the two level controllers. To preliminarily test if the motor can generate required power, a bench test was performed. The results show that the motor needs to be overpowered to achieve the required moment.

Powered Transtibial Prosthetic Device Control System Design, Implementation, and Bench Testing

2013 ◽  
Vol 8 (1) ◽  
Author(s):  
Jinming Sun ◽  
Philip A. Voglewede
Keyword(s):  
Digital Signal Processor ◽  
Control Algorithm ◽  
Controller Design ◽  
Digital Signal ◽  
Bench Test ◽  
Level Control ◽  
State Controller ◽  
Finite State ◽  
Dsp Control ◽  
Bench Testing

This article outlines the controller design for a specific active transtibial prosthesis. The controller governs the power output of a DC motor attached to a four-bar mechanism and torsional spring. Active power reinforcement is used to assist the push off at later stages of the stance phase and achieve ground clearance during the swing phase. A two level control algorithm which includes a higher level finite state controller and lower level proportional-integral-derivative (PID) controllers is applied. To implement this control algorithm, a digital signal processor (DSP) control board was used to realize the higher level control and an off-the-shelf motor controller was used to realize the lower level PID control. Sensors were selected to provide the desired feedback. A dynamic simulation was performed to obtain the proper PID parameters which were then utilized in a bench test to verify the approach.

scholarly journals FPGA Implementation for Rapid Prototyping of High Performance Voltage Source Inverters

2021 ◽  
Vol 6 (4) ◽  
pp. 320-331
Author(s):  
Yukun Luo ◽  
Keyword(s):  
Rapid Prototyping ◽  
Power Electronics ◽  
Code Generation ◽  
Digital Signal Processor ◽  
High Performance ◽  
Controller Design ◽  
Digital Signal ◽  
Current Control ◽  
Voltage Source ◽  
High Level

Field-programmable gate array (FPGA) is a powerful platform that can play an essential role in high-performance digital control of power electronics systems. However, the FPGA system’s design is quite different from that of a traditional microprocessor or a digital signal processor (DSP). Instead of sequential programming using high-level languages, such as C/C++, FPGA controller implementation requires a hardware description language (HDL) such as Verilog and VHDL, which requires extensive verification and optimization during the design process. This paper proposes a systematic FPGA design methodology with optimum resource utilization for rapid prototyping of high-performance power electronics applications to facilitate the widespread adoption of FPGA technology in power electronics. The FPGA controller design is concurrent with the power stage and utilizes high-level synthesis (HLS) tools and Simulink code generation toolbox. This paper covers the detailed design, implementation, and experimental validation of two specific applications, i.e., an active power filter (APF) and a motor emulator (ME), demonstrating the generalized features of the methodology. Employing fundamentally different control structures, both application examples achieve ultra-high current control bandwidth leveraging SiC MOSFETs switching at no less than 100 kHz.

scholarly journals Real-Time Fixed-Order LateralH2Controller for Micro Air Vehicle

2011 ◽  
Vol 2011 ◽  
pp. 1-15
Author(s):  
Meenakshi M. ◽  
M. Seetharama Bhat
Keyword(s):  
Real Time ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Micro Air Vehicle ◽  
Robust Performance ◽  
Optimal Projection ◽  
Air Vehicle ◽  
Hardware In Loop ◽  
Hardware In Loop Simulation ◽  
Low Order

This paper presents the design and development of a fixed low-order, robustH2controller for a micro air vehicle (MAV) named Sarika-2. The controller synthesis uses strengthened discrete optimal projection equations and frequency-dependent performance index to achieve robust performance and stability. A single fixed gain low-order dynamic controller provides simultaneous stabilization, disturbance rejection, and sensor noise attenuation over the entire flight speed range of 16 m/sec to 26 m/sec. Comparative study indicates that the low-orderH2-controller achieves robust performance levels similar to that of full order controller. Subsequently, the controller is implemented on a digital signal processor-based flight computer and is validated through the real time hardware in loop simulation. The responses obtained with hardware in loop simulation compares well with those obtained from the offline simulation.

scholarly journals Small-Signal Analysis and Control of Soft-Switching Naturally Clamped Snubberless Current-Fed Half-Bridge DC/DC Converter

2020 ◽  
Vol 10 (17) ◽  
pp. 6130
Author(s):  
Koyelia Khatun ◽  
Vakacharla Venkata Ratnam ◽  
Akshay Kumar Rathore ◽  
Beeramangalla Lakshminarasaiah Narasimharaju
Keyword(s):  
Digital Signal Processor ◽  
Signal Analysis ◽  
Controller Design ◽  
Design Procedure ◽  
Digital Signal ◽  
Soft Switching ◽  
Small Signal ◽  
Small Signal Analysis ◽  
Current Controller ◽  
The Stability

This paper presents small-signal analysis of a soft-switching naturally clamped snubberless isolated current-fed half-bridge (CFHB) DC-DC converter using state-space averaging. A two-loop average current controller was designed and implemented on a digital signal processor. The complete design procedure is presented here. Simulation results using software PSIM 11.1 are shown to validate the stability of the control system and the controller design. Experimental results for the step changes in load current vividly demonstrated satisfactory transient performance of the converter and validated the developed small-signal model and the control design.

scholarly journals Design and Implementation of a Speed-Loop-Periodic-Controller-Based Fault-Tolerant SPMSM Drive System

Energies ◽  
2019 ◽  
Vol 12 (19) ◽  
pp. 3593 ◽  
Author(s):  
Liu ◽  
Syahril Mubarok ◽  
Ridwan ◽  
Suwarno
Keyword(s):  
Hall Effect ◽  
Digital Signal Processor ◽  
Controller Design ◽  
Fault Tolerant ◽  
Permanent Magnet Synchronous Motor ◽  
Digital Signal ◽  
Drive System ◽  
Current Sensor ◽  
Insulated Gate Bipolar Transistor ◽  
Current Estimator

This paper proposes a speed-loop periodic controller design for fault-tolerant surface permanent magnet synchronous motor (SPMSM) drive systems. Faulty conditions, including an open insulated-gate bipolar transistor (IGBT), a short-circuited IGBT, or a Hall-effect current sensor fault are investigated. The fault-tolerant SPMSM drive system using a speed-loop periodic controller has better performance than when using a speed-loop PI controller under normal or faulty conditions. The superiority of the proposed speed-loop-periodic-controller-based SPMSM drive system includes faster transient responses and better load disturbance responses. A detailed design of the speed-loop periodic controller and its related fault-tolerant method, including fault detection, diagnosis, isolation, and control are included. In addition, a current estimator is also proposed to estimate the stator current. When the Hall-effect current sensor is faulty, the estimated current is used to replace the current of the faulty sensor. A 32-bit digital signal processor, type TMS-320F-2808, is used to execute the fault-tolerant method and speed-loop periodic control. Measured experimental results validate the theoretical analysis. The proposed implementation of a fault-tolerant SPMSM drive system and speed-loop periodic controller design can be easily applied in industry due to its simplicity.

Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

2000 ◽  
Author(s):  
Srikanth Perungulam ◽  
Scott Wills ◽  
Greg Mekras
Keyword(s):  
Cross Sections ◽  
Digital Signal Processor ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Digital Signal ◽  
Yield Enhancement ◽  
Final Conclusion ◽  
Stage Separation ◽  
Study Process

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

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