scholarly journals A Modified Signal Feed-Through Pulsed Flip- Flop for Low Power Applications

2017 ◽  
Vol 63 (3) ◽  
pp. 241-246 ◽  
Author(s):  
Ehsan Panahifar ◽  
Alireza Hassanzadeh
Keyword(s):  
Low Power ◽  
Input Data ◽  
Power Reduction ◽  
Leakage Power ◽  
Flip Flop ◽  
Dynamic Power ◽  
Pass Transistor ◽  
Power Delay Product ◽  
Hspice Simulation

AbstractIn this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.

scholarly journals A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 802
Author(s):  
Heng You ◽  
Jia Yuan ◽  
Weidi Tang ◽  
Zenghui Yu ◽  
Shushan Qiao
Keyword(s):  
Low Power ◽  
High Speed ◽  
Input Data ◽  
Low Voltage ◽  
Flip Flop ◽  
Sense Amplifier ◽  
Low Voltage Operation ◽  
Amplifier Stage ◽  
Simulation Results ◽  
Power Delay Product

In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

Various Logically Optimized D Flip Flop Circuits-A Comparative Study in Submicron Technology

2015 ◽  
Vol 4 (2) ◽  
Author(s):  
Abhijit Asthana ◽  
Shyam Akashe
Keyword(s):  
Comparative Study ◽  
Power Dissipation ◽  
Leakage Power ◽  
Simulation Test ◽  
Flip Flop ◽  
Chip Area ◽  
Low Leakage ◽  
Signal Systems ◽  
To Come ◽  
Power Delay Product

D-Flip Flop (D_FF) is a very important component of various digital, analog and mixed signal systems and designs. It is obvious to come up with optimized D_FF, that cater the needs of low leakage power, less power dissipation, less chip area on the chip and low delays. This paper presents a comparative study of various logically optimized circuits of D_FF using 8T, 11T, 12T and conventional 18T D_FF. The simulation, test circuits, schematics & layouts etc are done on Cadence Virtuoso tool in 180 nm technology. Designs are compared on grounds of power dissipation, leakage power, delays and power delay product.

A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power

Integration ◽  
2018 ◽  
Vol 60 ◽  
pp. 160-166 ◽  
Author(s):  
Ahmad Karimi ◽  
Abdalhossein Rezai ◽  
Mohammad Mahdi Hajhashemkhani
Keyword(s):  
Low Power ◽  
Leakage Power ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Power Pulse ◽  
Novel Design

Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits

2017 ◽  
Vol 16 (3) ◽  
pp. 867-874 ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Kavita Khare ◽  
Tarun K. Gupta ◽  
Nilay Khare
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Pass Transistor ◽  
Pass Transistor Logic

scholarly journals Low Glitch & Low Power Dual Edge Triggered DType Flip Flops for Integrated Applications

2019 ◽  
Vol 8 (2) ◽  
pp. 5906-5912
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Flip Flop ◽  
Silicon Area ◽  
Low Delay ◽  
Cadence Tool ◽  
Power Delay Product ◽  
Design Paper

This paper presents Dual Edge Triggered (DET) master slave D-Type flip flops for glitch free, low power, low delay, low silicon area and low Power Delay Product (PDP). This DET master slave D-Type flip flops are compared against the existing DET flip flops using 45nm & 180nm CMOS technology which has been simulated using Cadence Virtuoso. The proposed DET master slave D-Type flip flops has reduced the number of transistors in use for operation, which leads to low glitch, low power and low delay design. Paper consist glitch free DET master slave D-Type flip flops analysis for power, delay and PDP. The proposed DET flip flop is also simulated and implemented for 18nm Fin-FET in Cadence Tool.

scholarly journals Full Adder for Low Power Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 2682-2687
Keyword(s):  
Low Power ◽  
Processing System ◽  
Full Adder ◽  
Cmos Technology ◽  
Fundamental Operation ◽  
Dynamic Power ◽  
Power Delay Product ◽  
Electronic Processing

In an electronic processing system, addition of binary numbers is a fundamental operation. A one bit low power hybrid FA(full adder) is shown in showing performance improvisation by analysis and comparing with other conventional adders. 1 bit low power hybrid full adder is considered as a good way for enhancing the speed of the circuit in comparison with other conventional circuits of full adders. In that analysis paper, one bit low power hybrid FA(full adder) is implemented by EDA tool and the simulation is analysis by using generic 90nm CMOS technology at 5 volts and comparison is done at various voltages with other conventional full adders. For comparing 1 bit low power hybrid full adder with other conventional adders at various parameters such as static and dynamic power usage, delay & pdp (power delay product) are taken into consideration to show that 1 bit low power hybrid full adder is most suitable for various low power applications.

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