Aqueous Based Single Wafer Cleaning Process Development and Integration into 65nm Process Flow using Metal Hard Mask

2006 ◽  
Vol 914 ◽  
Author(s):  
Miao-Chun Lin ◽  
Mei-Qi Wang ◽  
Cheng-Ming Weng ◽  
Chopin Chou ◽  
JH Liao ◽  
...  
Keyword(s):  
Time Dependent ◽  
Metal Fluoride ◽  
Cleaning Process ◽  
Defect Modes ◽  
Hard Mask ◽  
Time Control ◽  
Wafer Cleaning ◽  
New Process ◽  
Low K ◽  
Electrical Data

AbstractAs the industry develops processes for the 65 and 45 nm technology nodes, post etch/ash cleaning faces new challenges with far more stringent requirements on surface cleanliness and materials loss. The introduction and integration of new materials, such as metal hard mask, creates additional requirements for wafer cleaning due to the occurrence of new defect modes related to metal hard mask. These include organometallic residue and metal fluorite compounds precipitating with time. We have developed a novel aqueous solution (AQ) based single wafer cleaning process to address these new defect modes. Physical characterization results and process integration electrical data and reliability data (TEM cross section review of the vias) are presented in this paper.The main conclusions can be summarized as follows: (1) In the dual damascene Cu/low-k process flow with hard mask, there are three typical residues after etch/ash: generic polymer residue, organometallic residue strongly bonded to metal maks, and time-dependent metal fluoride residue. (2) Generic polymer residue is very well characterized [1,2] and is usually easy to remove with solvent or aqueous solution [2,3]. (3)We developed an oxidizing chemistry based process to undercut the hard mask for the organometallic residue removal, which proved highly effective. (4)The time-dependent metal fluoride reside makes queue time control after etch/ash very critical (<1 hour). We developed a process with a fluorine based aqueous chemistry to address the metal fluoride residue, which proved highly effective. With this new process, queue time control is not required. (5) The post etch/ash cleaning for the Cu/low-k structure with metal hard mask typically employs the solvent/dry plasma ash multi-step procedure [4]. The new process developed in this research reduced the multi-step process to one wet clean step with two different aqueous chemistries in sequence. (6) The integration electrical data shows that the new single step aqueous cleaning process performance is comparable to, or even better than that from the solvent/dry plasma ash multi cleaning process. (7) Blanket Cu loss with the new process is about 23A/min, however TEM analysis of the vias after full integration shows Cu loss, we are working to improve the integration related Cu loss.

Metal Hard Mask Employed Cu/Low k Film Post Ash and Wet Clean Process Optimization and Integration into 65nm Manufacturing Flow

2007 ◽  
Vol 134 ◽  
pp. 359-362 ◽  
Author(s):  
Miao Chun Lin ◽  
Mei Qi Wang ◽  
Joe Lai ◽  
Ren Huang ◽  
Cheng Ming Weng ◽  
...  
Keyword(s):  
Mass Production ◽  
Process Integration ◽  
Cleaning Process ◽  
New Materials ◽  
Defect Modes ◽  
Hard Mask ◽  
Wafer Cleaning ◽  
New Challenges ◽  
Low K ◽  
Electrical Data

As 65nm technology in mass production and 45nm technology under development, post etch ash and cleaning faces new challenges with far more stringent requirements on surface cleanliness and materials loss. The introduction and integration of new materials, such as metal hard mask, creates additional requirements for wafer cleaning due to the occurrence of new defect modes related to metal hard mask. We have optimized a post etch ash process and developed a novel aqueous solution (AQ) based single wafer cleaning process to address these new defect modes. Physical characterization results and process integration electrical data are presented in this paper.

Industrial Challenges of TiN Hard Mask Wet Removal Process for 14nm Technology Node

2014 ◽  
Vol 219 ◽  
pp. 213-216 ◽  
Author(s):  
Akihisa Iwasaki ◽  
Kristell Courouble ◽  
Steven Lippy ◽  
Fabrice Buisine ◽  
Hidekazu Ishikawa ◽  
...  
Keyword(s):  
Time Dependent ◽  
Integration Scheme ◽  
Filling Process ◽  
Hard Mask ◽  
Technology Node ◽  
Immersion Lithography ◽  
Integration Schemes ◽  
193 Nm ◽  
Low K ◽  
Wet Removal

TiN Hard Mask (TiN-HM) integration scheme has been widely used for BEOL patterning in order to avoid ultra low-k (ULK) damage during plasma-ash process [1]. As the technology node advances, new integration schemes have to be used for the patterning of features below 80 nm pitch with 193 nm immersion lithography. In particular, thicker TiN-HM is necessary in order to ensure Self-Aligned-Via (SAV) integration which resolves via-metal short yield and TDDB issues caused by Litho-Etch-Litho-Etch (LELE) misalignment [2, 3]. The Cu filling process is significantly more difficult if the thick TiN is not removed because of the high aspect ratio of the structures. Moreover, with the use of TiN hard mask, a time-dependent crystal growth (TiCOF) residue may forms between line etch and metal deposition [4, 5], also hindering copper filling. Post-Etch-Treatment after line etching is one solution to the problem but N2plasma is not efficient enough to suppress the residue completely [6], and the CH4treatment proposed in [5] may be difficult to implement for 14 nm node, thus an efficient wet strip and clean provides a better solution.

Aqueous Based Single Wafer Cu/Low-k Cleaning Process Characterization and Integration into Dual Damascene Process Flow

2005 ◽  
Vol 103-104 ◽  
pp. 353-356
Author(s):  
Jian She Tang ◽  
Brian J. Brown ◽  
Steven Verhaverbeke ◽  
Han Wen Chen ◽  
Jim Papanu ◽  
...  
Keyword(s):  
Process Integration ◽  
Cleaning Process ◽  
Damascene Process ◽  
Wafer Cleaning ◽  
Process Characterization ◽  
Scale Down ◽  
Metallic Contaminants ◽  
Loss Control ◽  
Wet Etch ◽  
Low K

As device features scale down to 90nm and Cu/low-k films are employed for back end interconnects, post etch and ash residue cleaning becomes increasingly challenging due to the higher aspect ratio of the features, tighter CD control requirements, sensitivity of the low-k films, and the requirement for high wet etch selectivity between CuxO and Cu. Traditional solvent based cleaning in wet benches has additional issues such as wafer cross-contamination and high disposal cost [1, 2]. We have developed a novel aqueous solution (AQ) based single wafer cleaning process to address these challenges. The results of physical characterization, process integration electrical data, and process integration reliability data such as electromigration (EM) and stress migration data are presented. The main conclusions can be summarized as follows: (1) The single wafer cleaning process developed on the Oasis™ system can clean post etch residues and simultaneously clean the wafer front side and backside metallic contaminants; (2) In terms CuxO and Cu wet etch selectivity, CD loss control, the Oasis™ aqueous single wafer clean process is superior to the bench solvent cleaning process; (3)The Oasis aqueous cleaning process shows no undercut below etchstop due to the very low Cu etch amount in one cleaning pass, therefore the electromigration and stress migration performance of the aqueous Oasis processed wafers is clearly better than that of the solvent bench processed wafers.

Assessment of Reliability of cap layers used in Cu-Black DiamondTM Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Copper Ions ◽  
Dielectric Strength ◽  
Time Dependent ◽  
Breakdown Field ◽  
Field Range ◽  
Time Dependent Dielectric Breakdown ◽  
Voltage Ramp ◽  
Low K

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.

Effect of Dissolved Oxygen on Cu Corrosion in Single Wafer Cleaning Process

2009 ◽  
Vol 48 (4) ◽  
pp. 04C023 ◽  
Author(s):  
Masayoshi Imai ◽  
Yukinari Yamashita ◽  
Takashi Futatsuki ◽  
Morio Shiohara ◽  
Seiichi Kondo ◽  
...  
Keyword(s):  
Dissolved Oxygen ◽  
Cleaning Process ◽  
Wafer Cleaning ◽  
Cu Corrosion

Study of Static Electricity in Wafer Cleaning Process

2007 ◽  
Vol 134 ◽  
pp. 263-266 ◽  
Author(s):  
Masayuki Wada ◽  
T. Sueto ◽  
H. Takahashi ◽  
N. Hayashi ◽  
Atsuro Eitoku
Keyword(s):  
Cleaning Process ◽  
Static Electricity ◽  
Wafer Cleaning

Integration of Al-Fill Processes for Contacts and VIAS

1996 ◽  
Vol 427 ◽  
Author(s):  
H. J. Barth
Keyword(s):  
High Pressure ◽  
Chip Design ◽  
Size And Shape ◽  
Future Developments ◽  
Pattern Density ◽  
New Challenges ◽  
On Chip ◽  
Damascene Interconnects ◽  
Low K ◽  
Electrical Data

AbstractToday different Al-fill techniques are used for the fill of submicron contacts and vias. The integration aspects of the most promising approaches, Al-reflow, cold/hot Al-planarization and high pressure Al-fill (Forcefill) are compared to the widely used W-plug technique. The filling properties are discussed with respect to future applications in ULSI devices. Special attention is given to the barrier stability in contacts and the influence on patterning. Various electrical data and reliability results are compared to metallizations with W-plugs. The implications of the Al-fill processes on chip design, especially on the size and shape of holes, the pattern density, the possibility of producing stacked contacts/vias and the metal to contact/via overlap are considered also. In an outlook for future developments, e.g. the introduction of low k dielectrics, the inverse metallization architecture with (dual) damascene interconnects and the emerging Cu metallizations, Alfill processes are facing new challenges which will be discussed.

High-Performance Extremely Low-k Film Integration Technology with Metal Hard Mask Process for Cu Interconnects

2016 ◽  
Vol 5 (10) ◽  
pp. P578-P583 ◽  
Author(s):  
Naoki Torazawa ◽  
Susumu Matsumoto ◽  
Takeshi Harada ◽  
Yasunori Morinaga ◽  
Daisuke Inagaki ◽  
...  
Keyword(s):  
High Performance ◽  
Hard Mask ◽  
Integration Technology ◽  
Cu Interconnects ◽  
Low K

A Comparative Study for the Backside Illumination (BSI) Technology Using Bonding Wafer Cleaning Process for Advanced CMOS Image Sensor

2012 ◽  
Vol 195 ◽  
pp. 75-78
Author(s):  
Chung Kyung Jung ◽  
Sung Wook Joo ◽  
Seoung Hun Jeong ◽  
Sang Wook Ryu ◽  
Han Choon Lee ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Comparative Study ◽  
Quantum Efficiency ◽  
Wafer Bonding ◽  
Image Sensor ◽  
Silicon On Insulator ◽  
Cleaning Process ◽  
Electrochemical Systems ◽  
Wafer Cleaning ◽  
Direct Wafer Bonding

Over the last decades, the concept of backside illumination (BSI) sensors has become one of the leading solutions to optical challenges such as improved quantum efficiency (QE), and cross-talk, respectively [1-. Direct wafer bonding is a method for fabricating advanced substrates for micro-electrochemical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer.

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