A Study of Diffusion Barrier Characteristics of Electroless Co(W,P) Layers to Lead-free SnAgCu Solder

2009 ◽  
Vol 1156 ◽  
Author(s):  
Hung-Chun Pan ◽  
Tsung-Eong Hsieh
Keyword(s):  
Solid State ◽  
Diffusion Barrier ◽  
Liquid State ◽  
Flip Chip ◽  
Consumption Rate ◽  
Lead Free ◽  
Polycrystalline Structure ◽  
Snagcu Solder ◽  
Aging Test ◽  
Sac Solder

AbstractDiffusion barrier characteristics of amorphous and polycrystalline electroless Co(W,P) layers (α-Co(W,P) and poly-Co(W,P)) to lead-free SnAgCu (SAC) solder were investigated via the liquid- and solid-state aging tests. In the sample containing α-Co(W,P) subjected to liquid-state aging at 250°C for 1 hr, the spallation of (Co,Cu)Sn3 intermetallic compound (IMC) into the solder and formation of a polycrystalline P-rich layer in between SAC and Co(W,P) were found. Further, the α-Co(W,P) transforms into polycrystalline structure embedded with tiny Co2P precipitates As to the sample containing α-Co(W,P) subjected to solid-state aging at 150°C up to 1000 hrs, a thick (Cu,Co)6Sn5 IMC resided in between SAC and Co(W,P) and the P-rich layer beneath IMCs was similarly seen. In the samples containing poly-Co(W,P) subjected to liquid-state aging, a mixture of (Co,Cu)Sn3 and (Co,Ag)Sn3 IMCs formed in between SAC and Co(W,P). An amorphous W-rich layer formed in between SAC and poly-Co(W,P). Similar interfacial morphology was observed in the samples subjected to the solid-state aging test. Analytical results indicated the electroless Co(W,P) is in essential a combined-type, i.e., sacrificial-type plus stuffed-type, diffusion barrier. However, the α-Co(W,P) is a better diffusion barrier for under bump metallurgy (UBM) applications in flip-chip (FC) bonding since it exhibits a lower Co consumption rate in comparison with poly-Co(W,P).

Development of Lead-Free Flip Chip Package and Its Reliability

2003 ◽  
Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Wire Bonding ◽  
Point Of View ◽  
Lead Free ◽  
Temperature Cycle ◽  
Snagcu Solder ◽  
Temperature Cycle Test

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.

Optimization of Lead Free Plating for Flip Chip Applications

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001553-001602
Author(s):  
Charles L. Arvin ◽  
Jurg Stahl ◽  
Wolfgang Sauter ◽  
Harry cox ◽  
Eric Perfecto ◽  
...  
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Assembly Process ◽  
Solder Bumps ◽  
Free Solder ◽  
The Right ◽  
Pure Cu ◽  
Final Composition ◽  
Solder Composition ◽  
Sac Solder

Traditional flip chip processes have consolidated to a SnAgCu (SAC) solder system. Each company based upon their own needs and application space has come to their own method to achieve the desired final composition of the interconnect. These have included different solder compositions for both the pre-solder and the C4. The various interconnect solutions can range from no solder on one side such as pure Cu or Ni to an interconnect that has identical solder composition for both the substrate and the C4. Decisions for the optimized solution include the need for reliability, cost and yield. Picking the right solution also enables the elimination of defects such as solder voids, interfacial voids, white bumps, micro-solder bumps and non-wets. The optimized solutions are dependent upon many factors that include the fragility of the silicon dielectric, the size of the die, type of flux used at assembly, the assembly process used, method by which SnAg is plated such as various layering techniques, final processes steps in C4, test probe concepts, DSP methods and many more. In order to pick the appropriate scheme for each product and for each industry, it is imperative to know the interaction of all of these factors. This paper provides concepts and data about how to optimize assembly and lead free plating for a particular process. In the plating process, this includes the importance of various layering steps and analysis of incoming chemicals, especially the acids, and in the assembly process, the knowledge and matching of solder hierarchy, warpage, flux characteristics and preparation / cleaning steps prior to underfill. In particular, we will provide the data and the scheme by which it is possible to produce void free solder processes without bleed and feed on SnAg baths that are over 100 amp-hr per liter and over 1 year old.

scholarly journals Enhanced ferroelectric and piezoelectric performance of (Ba0.85Ca0.15)(Zr0.1Ti0.9)O3 lead-free ceramics upon Ce and Sb co-doping

RSC Advances ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 2616-2623
Author(s):  
Weijie Zheng ◽  
Jiaqi Lin ◽  
Xinmei Liu ◽  
Wenlong Yang ◽  
Yuanshuo Li
Keyword(s):  
Solid State ◽  
Solid State Reaction ◽  
Lead Free ◽  
Conventional Solid State Reaction ◽  
Co Doping ◽  
Lead Free Ceramics ◽  
Piezoelectric Performance

(Ba0.85Ca0.15)(Zr0.1Ti0.9−xCex)O3+ySb ceramics prepared by the conventional solid-state reaction.

A Comparative Study of Soldering Temperatures and Materials on the Reliability of Photovoltaic Modules

2012 ◽  
Vol 562-564 ◽  
pp. 188-191
Author(s):  
Keh Moh Lin ◽  
Yang Hsien Lee ◽  
Wen Yeong Huang ◽  
Po Chun Hsu ◽  
Chin Yang Huang ◽  
...  
Keyword(s):  
Comparative Study ◽  
Lead Free ◽  
Automatic Process ◽  
Lead Free Solder ◽  
Snagcu Solder ◽  
Photovoltaic Modules ◽  
Soldering Process ◽  
Different Temperatures ◽  
Free Solder

To find out the important factors which decisively affect the soldering quality of photovoltaic modules, solar cells were soldered under different conditions (different temperatures, PbSn vs. SnAgCu solder, manual vs. semi-automatic). Experimental results show that the soldering quality of PbSn under 350°C in the semi-automatic soldering process was quite stable while the soldering quality of lead-free solder was generally unacceptable in the manual or semi-automatic process under different temperatures. This result indicates that the soldering process with lead-free solder still needs to be further improved. It was also found that most cracks were formed on the interface between the solder and the silver paste and then expanded outwards.

Experimental evaluation of SnAgCu solder joint reliability in 100-μm pitch flip-chip assemblies

2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman
Keyword(s):  
Solder Joint ◽  
Experimental Evaluation ◽  
Flip Chip ◽  
Solder Joint Reliability ◽  
Snagcu Solder ◽  
Joint Reliability

Joining of Ti3SiC2 with Ti–6Al–4V Alloy

2002 ◽  
Vol 17 (1) ◽  
pp. 52-59 ◽  
Author(s):  
N.F. Gao ◽  
Y. Miyamoto
Keyword(s):  
Solid State ◽  
Rate Constant ◽  
Liquid State ◽  
Parabolic Rate Constant ◽  
Diffusion Path ◽  
Solid State Diffusion ◽  
Diffusion Controlled ◽  
State Diffusion ◽  
Rate Controlled ◽  
Higher Temperature

The joining of a Ti3SiC2 ceramic with a Ti–6Al–4V alloy was carried out at the temperature range of 1200–1400 °C for 15 min to 4 h in a vacuum. The total diffusion path of joining was determined to be Ti3SiC2/Ti5Si3Cx/Ti5Si3Cx + TiCx/TiCx/Ti. The reaction was rate controlled by the solid-state diffusion below 1350 °C and turned to the liquid-state diffusion controlled with a dramatic increase of parabolic rate constant Kp when the temperature exceeded 1350 °C. The TiCx tended to grow at the boundarywith the Ti–6Al–4V alloy at a higher temperature and longer holding time. TheTi3SiC2/Ti–6Al–4V joint is expected to be applied to implant materials.

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