Dopant Segregation at Polycrystalline Silicon Grain Boundaries in Device Fabrication Processes

1989 ◽  
Vol 164 ◽  
Author(s):  
M. Itoh ◽  
I. Aikawa ◽  
N. Hirashita ◽  
T. Ajioka
Keyword(s):  
Grain Boundaries ◽  
Polycrystalline Silicon ◽  
Annealing Temperature ◽  
Segregation Ratio ◽  
Device Fabrication ◽  
Phosphorus Concentration ◽  
Cross Sectional ◽  
Dopant Segregation ◽  
Linear Relationships ◽  
Si Films

AbstractThe dopant segregation at the polycrystalline silicon grain boundaries in device fabrication processes has been studied with a new approach using spreading resistance(SR) measurement, SIMS and cross-sectional TEM(XTEM). Phosphorus implanted LPCVD poly-Si films were annealed at 900°C-1000°C in N2 for 30min. Electrically active dopant concentrations obtained from SR measurements are constant in depth within the poly-Si films. On the other hand, the phosphorus concentration measured by SIMS is found to increase with increasing depth and to have linear relationships to reciprocal grain sizes observed by XTEM for all poly-Si films. The linear relationship indicates that the number of segregated phosphorus atoms per unit grain surface area at the grain boundaries is uniform throughout poly-Si films. Both phosphorus concentrations in the grains and at the grain boundaries are evaluated. The heat of segregation of 1.7eV is obtained from the annealing temperature dependence of the segregation ratio. Our results indicate that carrier concentration in the poly-Si film is more sensitive to annealing temperature in device fabrication processes. The carries concentration is determined by kinetics rather than by equilibrium segregation of dopants.

scholarly journals Characterization of Defects and Stress in Polycrystalline Silicon Thin Films on Glass Substrates by Raman Microscopy

2011 ◽  
Vol 2011 ◽  
pp. 1-14 ◽  
Author(s):  
Kuninori Kitahara ◽  
Toshitomo Ishii ◽  
Junki Suzuki ◽  
Takuro Bessyo ◽  
Naoki Watanabe
Keyword(s):  
Grain Boundaries ◽  
Polycrystalline Silicon ◽  
Solid Phase ◽  
Raman Microscopy ◽  
Laser Crystallization ◽  
Local Vibration ◽  
Optical Phonon Mode ◽  
Glass Substrates ◽  
Silicon Thin Films ◽  
Si Films

Raman microscopy was applied to characterize polycrystalline silicon (poly-Si) on glass substrates for application as thin-film transistors (TFTs) integrated on electronic display panels. This study examines the crystallographic defects and stress in poly-Si films grown by industrial techniques: solid phase crystallization and excimer laser crystallization (ELC). To distinguish the effects of defects and stress on the optical-phonon mode of the Si–Si bond, a semiempirical analysis was performed. The analysis was compared with defect images obtained through electron microscopy and atomic force microscopy. It was found that the Raman intensity for the ELC film is remarkably enhanced by the hillocks and ridges located around grain boundaries, which indicates that Raman spectra mainly reflect the situation around grain boundaries. A combination of the hydrogenation of films and the observation of the Si-hydrogen local-vibration mode is useful to support the analysis on the defects. Raman microscopy is also effective for detecting the plasma-induced damage suffered during device processing and characterizing the performance of Si layer in TFTs.

The Effect of Heat Treatment on Grain Boundary Properties in Cast Polycrystalline Silicon

1981 ◽  
Vol 5 ◽  
Author(s):  
P.E. Russell ◽  
C.R. Herrington ◽  
D.E. Burke ◽  
P.H. Holloway
Keyword(s):  
Heat Treatment ◽  
Grain Boundary ◽  
Grain Boundaries ◽  
Polycrystalline Silicon ◽  
Surface Recombination ◽  
Device Fabrication ◽  
Solar Cell Device ◽  
Device Structure ◽  
Heat Treated ◽  
Boundary Properties

ABSTRACTThe effects of heat treatment at temperatures appropriate for solar cell device fabrication on grain boundaries in cast poicrystalline silicon have been studied. An MIS device structure using a 200° C heating was used for fabricating test devices on heat treated samples for EBIC studies. Grain boundary effective surface recombination velocities (Seffgb ) and effective mid-grain diffusion lengths were measured. Seffgb was found to increase after heat treatment. Segregation of oxygen to grain boundaries has been observed in heat treated samples.

The Effects of Cu on Field Aided Lateral Crystallization (FALC) of Amorphous Silicon (a-Si) Films

2001 ◽  
Vol 664 ◽  
Author(s):  
Jae-Bok Lee ◽  
Chul-Ho Kim ◽  
Se-Youl Kwon ◽  
Duck-Kyun Choi
Keyword(s):  
Electric Field ◽  
Amorphous Silicon ◽  
Applied Field ◽  
Polycrystalline Silicon ◽  
Annealing Temperature ◽  
Negative Electrode ◽  
Free Region ◽  
Lateral Crystallization ◽  
Novel Concept ◽  
Si Films

ABSTRACTA novel concept of field aided lateral crystallization (FALC) and the effects of Cu on FALC of amorphous silicon (a-Si) were investigated. Cu was found to induce the lateral crystallization toward a metal-free region as well as the crystallization of a-Si in contact with Cu. In particular, the lateral crystallization caused by Cu was noticeably accelerated at the negative electrode side in every pattern with an aid of electric field, while it was retarded at the positive electrode side. The occurrence of Cu-FALC phenomenon was interpreted in terms of dominant diffusing species (DDS) in the reaction between metal and Si. The FALC velocity increased with the applied field intensity and the annealing temperature. The crystallization of a-Si was achieved at temperatures as low as 375°C when the annealing time increased in the presence of high electric field, above 30V/cm. Therefore, we could demonstrate the possibility of low temperature (<500°C) polycrystalline silicon (poly-Si) crystallization using Cu as a mediator in FALC technology.

Kinetics and Microstructure of Transiently Annealed Implanted Polycrystalline Silicon Layers

1989 ◽  
Vol 157 ◽  
Author(s):  
J.M.C. England ◽  
P.J. Timans ◽  
R.A. Mcmahon ◽  
H. Ahmed ◽  
C. Hill ◽  
...  
Keyword(s):  
Grain Size ◽  
Polycrystalline Silicon ◽  
Annealing Temperature ◽  
Solid Phase ◽  
Interface Roughness ◽  
Cross Sectional ◽  
Time Resolved ◽  
Microstructural Changes ◽  
Transmission Electron

ABSTRACTMicrostructural changes occurring during the early stages of rapid thermal annealing of polycrystalline silicon bipolar emitters crucially affect the final dopant distribution and hence the performance of these devices. The first stage of annealing is epitaxial regrowth in the solid phase of the layer amorphised by the implantation. In-situ studies using time-resolved reflectivity measurements, combined with cross-sectional transmission electron microscopy of partly annealed structures, have determined the effects of initial grain size, annealing temperature and amorphising species (Si or As) on the rate of regrowth and the microstructural changes which occur during annealing. As the grain size is reduced, the regrowth rate decreases and the interface roughness increases. Arsenic implantation alters the rate of regrowth in such a manner as to produce a smoother interface than that in silicon implanted material.

Growth of near noble metal Pd and Pt thin film silicides morphology and structure

1984 ◽  
Vol 42 ◽  
pp. 498-499
Author(s):  
E. I. Alessandrini ◽  
M. O. Aboelfotoh
Keyword(s):  
Noble Metals ◽  
Annealing Temperature ◽  
Chemical Compounds ◽  
Barrier Properties ◽  
Solid State Reactions ◽  
Transmission Electron ◽  
Stable Chemical ◽  
Metal Thickness ◽  
Amorphous Si ◽  
Si Films

Considerable interest has been generated in solid state reactions between thin films of near noble metals and silicon. These metals deposited on Si form numerous stable chemical compounds at low temperatures and have found applications as Schottky barrier contacts to silicon in VLSI devices. Since the very first phase that nucleates in contact with Si determines the barrier properties, the purpose of our study was to investigate the silicide formation of the near noble metals, Pd and Pt, at very thin thickness of the metal films on amorphous silicon.Films of Pd and Pt in the thickness range of 0.5nm to 20nm were made by room temperature evaporation on 40nm thick amorphous Si films, which were first deposited on 30nm thick amorphous Si3N4 membranes in a window configuration. The deposition rate was 0.1 to 0.5nm/sec and the pressure during deposition was 3 x 10 -7 Torr. The samples were annealed at temperatures in the range from 200° to 650°C in a furnace with helium purified by hot (950°C) Ti particles. Transmission electron microscopy and diffraction techniques were used to evaluate changes in structure and morphology of the phases formed as a function of metal thickness and annealing temperature.

scholarly journals Dopant-segregation to grain boundaries controls electrical conductivity of n-type NbCo(Pt)Sn half-Heusler alloy mediating thermoelectric performance

2021 ◽  
pp. 117147
Author(s):  
Ting Luo ◽  
Federico Serrano-Sánchez ◽  
Hanna Bishara ◽  
Siyuan Zhang ◽  
Ruben Bueno Villoro ◽  
...  
Keyword(s):  
Electrical Conductivity ◽  
Grain Boundaries ◽  
Heusler Alloy ◽  
Thermoelectric Performance ◽  
Dopant Segregation

scholarly journals Optimizing the Properties of La0.8Sr0.2CrO3 Thin Films through Post-Annealing for High-Temperature Sensing

Nanomaterials ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 1802
Author(s):  
Dan Liu ◽  
Peng Shi ◽  
Yantao Liu ◽  
Yijun Zhang ◽  
Bian Tian ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Films ◽  
Annealing Temperature ◽  
Rf Sputtering ◽  
Maximum Size ◽  
Cross Sectional ◽  
Post Annealing ◽  
Maximum Conductivity ◽  
Different Temperatures ◽  
Post Annealing Temperature

La0.8Sr0.2CrO3 (0.2LSCO) thin films were prepared via the RF sputtering method to fabricate thin-film thermocouples (TFTCs), and post-annealing processes were employed to optimize their properties to sense high temperatures. The XRD patterns of the 0.2LSCO thin films showed a pure phase, and their crystallinities increased with the post-annealing temperature from 800 °C to 1000 °C, while some impurity phases of Cr2O3 and SrCr2O7 were observed above 1000 °C. The surface images indicated that the grain size increased first and then decreased, and the maximum size was 0.71 μm at 1100 °C. The cross-sectional images showed that the thickness of the 0.2LSCO thin films decreased significantly above 1000 °C, which was mainly due to the evaporation of Sr2+ and Cr3+. At the same time, the maximum conductivity was achieved for the film annealed at 1000 °C, which was 6.25 × 10−2 S/cm. When the thin films post-annealed at different temperatures were coupled with Pt reference electrodes to form TFTCs, the trend of output voltage to first increase and then decrease was observed, and the maximum average Seebeck coefficient of 167.8 µV/°C was obtained for the 0.2LSCO thin film post-annealed at 1100 °C. Through post-annealing optimization, the best post-annealing temperature was 1000 °C, which made the 0.2LSCO thin film more stable to monitor the temperatures of turbine engines for a long period of time.

Grain Boundary Atomic Structures in SrTiO3 and BaTiO3

2007 ◽  
Vol 558-559 ◽  
pp. 851-856 ◽  
Author(s):  
Takahisa Yamamoto ◽  
Teruyasu Mizoguchi ◽  
S.Y. Choi ◽  
Yukio Sato ◽  
Naoya Shibata ◽  
...  
Keyword(s):  
Grain Boundary ◽  
Grain Boundaries ◽  
Annealing Temperature ◽  
Unit Length ◽  
Rate Dependency ◽  
Atomic Structures ◽  
Current Voltage ◽  
Single Grain ◽  
Current Voltage Characteristics ◽  
Theoretical Results

SrTiO3 bicrystals with various types of grain boundaries were prepared by joining two single crystals at high temperature. By using the bicrystals, we examined their current-voltage characteristics across single grain boundaries from a viewpoint of point defect segregation in the vicinity of the grain boundaries. Current-voltage property in SrTiO3 bicrystals was confirmed to show a cooling rate dependency from annealing temperature, indicating that cation vacancies accumulate due to grain boundary oxidation. The theoretical results obtained by ab-initio calculation clearly showed that the formation energy of Sr vacancies is the lowest comparing with Ti and O vacancies in oxidized atomosphere. The formation of a double Schottky barrier (DSB) in n-type SrTiO3 is considered to be closely related to the accumulation of the charged Sr vacancies. Meanwhile, by using three types of low angle boundaries, the excess charges related to one grain boundary dislocation par unit length was estimated. In this study, we summarized our results obtained in our group.

Low-Temperature LPCVD MEMS Technologies

2002 ◽  
Vol 729 ◽  
Author(s):  
Roger T. Howe ◽  
Tsu-Jae King
Keyword(s):  
Silicon Germanium ◽  
Polycrystalline Silicon ◽  
Rf Mems ◽  
Sige Layer ◽  
Copper Metallization ◽  
Si Films ◽  
P Type ◽  
Mems Process ◽  
Post Deposition

AbstractThis paper describes recent research on LPCVD processes for the fabrication of high-quality micro-mechanical structures on foundry CMOS wafers. In order to avoid damaging CMOS electronics with either aluminum or copper metallization, the MEMS process temperatures should be limited to a maximum of 450°C. This constraint rules out the conventional polycrystalline silicon (poly-Si) as a candidate structural material for post-CMOS integrated MEMS. Polycrystalline silicon-germanium (poly-SiGe) alloys are attractive for modular integration of MEMS with electronics, because they can be deposited at much lower temperatures than poly-Si films, yet have excellent mechanical properties. In particular, in-situ doped p-type poly-SiGe films deposit rapidly at low temperatures and have adequate conductivity without post-deposition annealing. Poly-Ge can be etched very selectively to Si, SiGe, SiO2 and Si3N4 in a heated hydrogen peroxide solution, and can therefore be used as a sacrificial material to eliminate the need to protect the CMOS electronics during the MEMS-release etch. Low-resistance contact between a structural poly-SiGe layer and an underlying CMOS metal interconnect can be accomplished by deposition of the SiGe onto a typical barrier metal exposed in contact windows. We conclude with directions for further research to develop poly-SiGe technology for integrated inertial, optical, and RF MEMS applications.

Sign in / Sign up

Export Citation Format

Share Document