Electrical Reliability of Cu and Low-K Dielectric Integration

1998 ◽  
Vol 511 ◽  
Author(s):  
S. Simon Wong ◽  
Alvin L. S. Loke ◽  
Jeffrey T. Wetzel ◽  
Paul H. Townsend ◽  
Raymond N. Vrtis ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Hole Injection ◽  
Barrier Materials ◽  
Cu Metallization ◽  
Arylene Ether ◽  
Fluorinated Polyimide ◽  
Drift Behavior ◽  
Bias Temperature Stress ◽  
Electrical Reliability ◽  
Low K

ABSTRACTThe recent demonstrations of manufacturable multilevel Cu metallization have heightened interest to integrate Cu and low-K dielectrics for future integrated circuits. For reliable integration of both materials, Cu may need to be encapsulated by barrier materials since Cu ions (Cu+) might drift through low-K dielectrics to degrade interconnect and device integrity. This paper addresses the use of electrical testing techniques to evaluate the Cu+ drift behavior of low-K polymer dielectrics. Specifically, bias-temperature stress and capacitance-voltage measurements are employed as their high sensitivities are well-suited for examining charge instabilities in dielectrics. Charge instabilities other than Cu+ drift also exist. For example, when low-K polymers come into direct contact with either a metal or Si, interface-related instabilities attributed to electron/hole injection are observed. To overcome these issues, a planar Cu/oxide/polymer/oxide/Si capacitor test structure is developed for Cu+ drift evaluation. Our study shows that Cu+ ions drift readily into poly(arylene ether) and fluorinated polyimide, but much more slowly into benzocyclobutene. A thin nitride cap layer can prevent the penetration.

Evaluation of Copper Penetration in Low-κ Polymer Dielectrics by Bias-Temperature Stress

1999 ◽  
Vol 565 ◽  
Author(s):  
Alvin L. S. Loke ◽  
S. Simon Wong ◽  
Niranjan A. Talwalkar ◽  
Jeffrey T. Wetzel ◽  
Paul H. Townsend ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Copper Ions ◽  
Organic Polymer ◽  
Qualitative Comparison ◽  
Current Time ◽  
Chemical Structures ◽  
Arylene Ether ◽  
Fluorinated Polyimide ◽  
Polymer Dielectrics ◽  
Bias Temperature Stress

AbstractThe industry is strongly interested in integrating low-κ dielectrics with Damascene copper. Otherwise, with conventional materials, interconnects cannot continue to scale without limiting circuit performance. Integration of copper wiring with silicon dioxide (oxide) requires barrier encapsulation since copper drifts readily in oxide. An important aspect of integrating copper wiring with low-κ dielectrics is the drift behavior of copper ions in these dielectrics, which will directly impact the barrier requirements and hence integration complexity.This work evaluates and compares the copper drift properties in six low-κ organic polymer dielectrics: parylene-F; benzocyclobutene; fluorinated polyimide; an aromatic hydrocarbon; and two varieties of poly(arylene ether). Copper/oxide/polymer/oxide/silicon capacitors are subjected to bias-temperature stress to accelerate penetration of copper from the gate electrode into the polymer. The oxide-sandwiched dielectric stack is used to overcome interface instabilities occurring when a low-κ dielectric is in direct contact with either the gate metal or silicon substrate. The copper drift rates in the various polymers are estimated by electrical techniques, including capacitance-voltage, current-voltage, and current-time measurements. Results correlate well with timeto-breakdown obtained by stressing the capacitor dielectrics. Our study shows that copper ions drift readily into fluorinated polyimide and poly(arylene ether), more slowly into parylene-F, and even more slowly into benzocyclobutene. A qualitative comparison of the chemical structures of the polymers suggests that copper drift in these polymers may possibly be retarded by increased crosslinking and enhanced by polarity in the polymer.

Evaluation of Copper Penetration in Low-κ Polymer Dielectrics by Bias-Temperature Stress

1999 ◽  
Vol 564 ◽  
Author(s):  
Alvin L. S. Loke ◽  
S. Simon Wong ◽  
Niranjan A. Talwalkar ◽  
Jeffrey T. Wetzel ◽  
Paul H. Townsend ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Copper Ions ◽  
Organic Polymer ◽  
Qualitative Comparison ◽  
Current Time ◽  
Chemical Structures ◽  
Arylene Ether ◽  
Fluorinated Polyimide ◽  
Polymer Dielectrics ◽  
Bias Temperature Stress

AbstractThe industry is strongly interested in integrating low–κ dielectrics with Damascene copper. Otherwise, with conventional materials, interconnects cannot continue to scale without limiting circuit performance. Integration of copper wiring with silicon dioxide (oxide) requires barrier encapsulation since copper drifts readily in oxide. An important aspect of integrating copper wiring with low-K dielectrics is the drift behavior of copper ions in these dielectrics, which will directly impact the barrier requirements and hence integration complexity.This work evaluates and compares the copper drift properties in six low-κ organic polymer dielectrics: parylene-F; benzocyclobutene; fluorinated polyimide; an aromatic hydrocarbon; and two varieties of poly(arylene ether). Copper/oxide/polymer/oxide/silicon capacitors are subjected to bias-temperature stress to accelerate penetration of copper from the gate electrode into the polymer. The oxide-sandwiched dielectric stack is used to overcome interface instabilities occurring when a low-κ dielectric is in direct contact with either the gate metal or silicon substrate. The copper drift rates in the various polymers are estimated by electrical techniques, including capacitance- voltage, current-voltage, and current-time measurements. Results correlate well with timeto- breakdown obtained by stressing the capacitor dielectrics. Our study shows that copper ions drift readily into fluorinated polyimide and poly(arylene ether), more slowly into parylene-F, and even more slowly into benzocyclobutene. A qualitative comparison of the chemical structures of the polymers suggests that copper drift in these polymers may possibly be retarded by increased crosslinking and enhanced by polarity in the polymer.

Novel Epoxy Siloxane Polymer as Low-K Dielectric

2004 ◽  
Vol 812 ◽  
Author(s):  
Pei-I Wang ◽  
Jasbir S. Juneja ◽  
Shyam Murarka ◽  
Toh –Ming Lu ◽  
Ram Ghoshal ◽  
...  
Keyword(s):  
Current Density ◽  
Dielectric Material ◽  
Curing Temperature ◽  
Breakdown Field ◽  
Barrier Materials ◽  
Siloxane Polymer ◽  
Stress Cycles ◽  
Bias Temperature Stress ◽  
Low K ◽  
Applied Electrical Field

AbstractThis paper introduces a low-k dielectric material, a novel epoxy siloxane polymer, made by Polyset Co. Inc, which has promising properties. The polymer was spin-deposited, and thickness and optical properties were measured using variable-angle spectroscopic ellipsometry (VASE). Fourier transform infrared (FTIR) spectra of as deposited and cured polymers showed that the polymer is fully cured at 165 °C. The low curing temperature of the polymer lowers stress in back-end-of-line (BEOL) stack and thus improves the reliability. The polymer is thermally stable up to 400 °C. The polymer has Young's modulus of ∼5 GPa and hardness of greater than 0.4 GPa. After multiple stress cycles up to 300 °C, the residual stress in the polymer at room temperature is less than 60 Mpa. The polymer has good adhesion with semiconductor and dielectrics such as Si, SiC, and SiO2, metals such as Al, Cu, Co, and W, and barrier materials such as TaN. The bulk dielectric constant of the polymer is 2.4 - 2.7. The leakage current density in the polymer at the applied electrical field of 1 MV/cm is in 10−9 A/cm2 range and the breakdown field of the polymer is ranging from 5 to 7 MV/cm. The polymer when subjected to bias-temperature stress (BTS) conditions of 150 °C and 0.5 MV/cm shows no C-V shift for up to 100 min indicating that the polymer resists Copper diffusion. The current density under stress conditions of 150 °C and 0.5 MV/cm was less than 10−9 A/cm2 for up to 7 hrs.

Analytical electron microscopy of grain boundaries in Al-Cu metallizations

1992 ◽  
Vol 50 (2) ◽  
pp. 1684-1685
Author(s):  
J. R. Michael ◽  
A. D. Romig ◽  
D. R. Frear
Keyword(s):  
Electron Microscopy ◽  
Integrated Circuits ◽  
Failure Mode ◽  
Current Density ◽  
Thermal History ◽  
Analytical Electron Microscopy ◽  
Cu Metallization ◽  
Analytical Electron ◽  
Interconnect Lines

Al with additions of Cu is commonly used as the conductor metallizations for integrated circuits, the Cu being added since it improves resistance to electromigration failure. As linewidths decrease to submicrometer dimensions, the current density carried by the interconnect increases dramatically and the probability of electromigration failure increases. To increase the robustness of the interconnect lines to this failure mode, an understanding of the mechanism by which Cu improves resistance to electromigration is needed. A number of theories have been proposed to account for role of Cu on electromigration behavior and many of the theories are dependent of the elemental Cu distribution in the interconnect line. However, there is an incomplete understanding of the distribution of Cu within the Al interconnect as a function of thermal history. In order to understand the role of Cu in reducing electromigration failures better, it is important to characterize the Cu distribution within the microstructure of the Al-Cu metallization.

Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

2002 ◽  
Vol 716 ◽  
Author(s):  
Ilanit Fisher ◽  
Wayne D. Kaplan ◽  
Moshe Eizenberg ◽  
Michael Nault ◽  
Timothy Weidman
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Hydrogen Plasma ◽  
Porous Silica ◽  
Film Deposition ◽  
Copper Metallization ◽  
High Porosity ◽  
Tem Analysis ◽  
Chip Technology ◽  
Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

Delamination Behavior of Cu-Low-k Stack Under Different Slurries

2003 ◽  
Vol 767 ◽  
Author(s):  
A. K. Sikder ◽  
S. Thagella ◽  
P. B. Zantye ◽  
Ashok Kumar
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Chemical Mechanical Polishing ◽  
Wear Behavior ◽  
Polished Surface ◽  
Cu Metallization ◽  
Wide Range ◽  
Low K ◽  
Delamination Behavior ◽  
Scanning Electron

AbstractLower mechanical strength, reduced cohesive strength and lack of compatibility with other interconnect materials, are the major challenges involved in chemical mechanical polishing (CMP) of Cu metallization with ultra low-k materials as interlayer dielectrics. In this study we have investigated the polishing behavior of patterned Cu samples with underneath different low-k materials using two different slurries and a wide range of machine parameters. CMP micro tribometer was used to polish the samples with different rotations of platen (50 to 250 RPM) and down forces (1-6 PSI). Friction co-efficient and wear behavior were also investigated at different conditions. Optical and scanning electron microscopy was used to investigate the polished surface. It was observed that the two different Cu slurries used for polishing have marked effects on the polishing of Cu-low-k stack with respect to wear and delamination.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

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