Novel Epoxy Siloxane Polymer as Low-K Dielectric

2004 ◽  
Vol 812 ◽  
Author(s):  
Pei-I Wang ◽  
Jasbir S. Juneja ◽  
Shyam Murarka ◽  
Toh –Ming Lu ◽  
Ram Ghoshal ◽  
...  
Keyword(s):  
Current Density ◽  
Dielectric Material ◽  
Curing Temperature ◽  
Breakdown Field ◽  
Barrier Materials ◽  
Siloxane Polymer ◽  
Stress Cycles ◽  
Bias Temperature Stress ◽  
Low K ◽  
Applied Electrical Field

AbstractThis paper introduces a low-k dielectric material, a novel epoxy siloxane polymer, made by Polyset Co. Inc, which has promising properties. The polymer was spin-deposited, and thickness and optical properties were measured using variable-angle spectroscopic ellipsometry (VASE). Fourier transform infrared (FTIR) spectra of as deposited and cured polymers showed that the polymer is fully cured at 165 °C. The low curing temperature of the polymer lowers stress in back-end-of-line (BEOL) stack and thus improves the reliability. The polymer is thermally stable up to 400 °C. The polymer has Young's modulus of ∼5 GPa and hardness of greater than 0.4 GPa. After multiple stress cycles up to 300 °C, the residual stress in the polymer at room temperature is less than 60 Mpa. The polymer has good adhesion with semiconductor and dielectrics such as Si, SiC, and SiO2, metals such as Al, Cu, Co, and W, and barrier materials such as TaN. The bulk dielectric constant of the polymer is 2.4 - 2.7. The leakage current density in the polymer at the applied electrical field of 1 MV/cm is in 10−9 A/cm2 range and the breakdown field of the polymer is ranging from 5 to 7 MV/cm. The polymer when subjected to bias-temperature stress (BTS) conditions of 150 °C and 0.5 MV/cm shows no C-V shift for up to 100 min indicating that the polymer resists Copper diffusion. The current density under stress conditions of 150 °C and 0.5 MV/cm was less than 10−9 A/cm2 for up to 7 hrs.

Electrical Reliability of Cu and Low-K Dielectric Integration

1998 ◽  
Vol 511 ◽  
Author(s):  
S. Simon Wong ◽  
Alvin L. S. Loke ◽  
Jeffrey T. Wetzel ◽  
Paul H. Townsend ◽  
Raymond N. Vrtis ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Hole Injection ◽  
Barrier Materials ◽  
Cu Metallization ◽  
Arylene Ether ◽  
Fluorinated Polyimide ◽  
Drift Behavior ◽  
Bias Temperature Stress ◽  
Electrical Reliability ◽  
Low K

ABSTRACTThe recent demonstrations of manufacturable multilevel Cu metallization have heightened interest to integrate Cu and low-K dielectrics for future integrated circuits. For reliable integration of both materials, Cu may need to be encapsulated by barrier materials since Cu ions (Cu+) might drift through low-K dielectrics to degrade interconnect and device integrity. This paper addresses the use of electrical testing techniques to evaluate the Cu+ drift behavior of low-K polymer dielectrics. Specifically, bias-temperature stress and capacitance-voltage measurements are employed as their high sensitivities are well-suited for examining charge instabilities in dielectrics. Charge instabilities other than Cu+ drift also exist. For example, when low-K polymers come into direct contact with either a metal or Si, interface-related instabilities attributed to electron/hole injection are observed. To overcome these issues, a planar Cu/oxide/polymer/oxide/Si capacitor test structure is developed for Cu+ drift evaluation. Our study shows that Cu+ ions drift readily into poly(arylene ether) and fluorinated polyimide, but much more slowly into benzocyclobutene. A thin nitride cap layer can prevent the penetration.

Interface Stability of Metal Barrier and low K Dielectrics

2007 ◽  
Vol 990 ◽  
Author(s):  
Toh-Ming Lu ◽  
Y. Ou ◽  
P.-I. Wang
Keyword(s):  
Metal Ions ◽  
Refractory Metal ◽  
Dielectric Material ◽  
Dielectric Materials ◽  
Processing Temperature ◽  
Electrical Stress ◽  
Bias Temperature Stress ◽  
Electric Filed ◽  
Low K ◽  
Metal Barrier

ABSTRACTIt is known that the interface between a refractory metal barrier and a dielectric material is stable against thermal treatment at a conventional IC interconnect processing temperature. However, the interface may not be stable against thermal and electrical stress called the bias temperature stress (BTS) at moderate conditions of 150 °C and 0.5 MV/cm. Massive refractory metal ions are seen to drift into low K dielectric materials that contain a mixture of organic and inorganic elements. It is argued that the oxidation of the metal at the interface creates unstable metal ions that are ready to drift into the dielectric film under an electric filed during the BTS test. Dielectric or dielectric capping materials that do not contain oxygen can prevent metal oxidation and are desirable to create a stable metal and dielectric interface.

Assessment of Reliability of cap layers used in Cu-Black DiamondTM Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Copper Ions ◽  
Dielectric Strength ◽  
Time Dependent ◽  
Breakdown Field ◽  
Field Range ◽  
Time Dependent Dielectric Breakdown ◽  
Voltage Ramp ◽  
Low K

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.

The Study of Fluorinated Amorphous Carbon as Low-K Dielectric Material and its Interface with Copper Metallization

1999 ◽  
Vol 565 ◽  
Author(s):  
N. Ariel ◽  
M. Eizenberg ◽  
E. Y. Tzou
Keyword(s):  
Amorphous Carbon ◽  
Nuclear Reactions ◽  
Dielectric Material ◽  
Copper Metallization ◽  
Limiting Factor ◽  
Adhesion Promoter ◽  
Adhesion Promotion ◽  
High Resolution Tem ◽  
Rc Delay ◽  
Low K

AbstractIn order to achieve better performance of devices, the interconnects RC delay time, the limiting factor of the device speed today, must be reduced. This calls for a new interconnect stack: lower resistivity Copper and low k materials (k<3) as dielectrics.Fluorinated amorphous carbon (a-F:C) prepared by HDP- CVD is an attractive candidate as a low-k material. In this work we have studied the film, its stability and its interface with Copper metallization. The high density plasma CVD process resulted in a film which contains C and F at a ratio of 1:0.6 as determined by Nuclear Reactions Analysis. XPS analysis of the Cls transition indicated four types of bonds: C-C, C-CF, CF, and CF2. X-ray diffraction as well as high resolution TEM analyses proved that the film was amorphous at least up to 500°C anneal. For various applications, the advantage of adding a thin bi-layer of a-SiC/SiOx for adhesion promotion purposes was demonstrated. In addition, the interface of a-F:C and the adhesion promoter layer with Ta, TaN and Cu was studied. No interdiffusion was observed by SIMS after 400°C annealing. 500°C annealing caused F outdiffusion from the film and Cu diffusion into the adhesion promoter layer.

scholarly journals High drain-current-density and high breakdown-field Al0.36Ga0.64N-channel heterojunction filed-effect transistors with a dual AlN/AlGaInN barrier layer

2022 ◽  
Author(s):  
Akiyoshi Inoue ◽  
Sakura Tanaka ◽  
Takashi Egawa ◽  
Makoto Miyoshi
Keyword(s):  
Current Density ◽  
Barrier Layer ◽  
Ohmic Contacts ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Device Fabrication ◽  
Breakdown Field ◽  
Field Plate ◽  
Order Of Magnitude ◽  
State Breakdown

Abstract In this study, we fabricated and characterized heterojunction field-effect transistors (HFETs) based on an Al0.36Ga0.64N-channel heterostructure with a dual AlN/AlGaInN barrier layer. The device fabrication was accomplished by adopting a regrown n++-GaN layer for ohmic contacts. The fabricated HFETs with a gate length of 2 μm and a gate-to-drain distance of 6 μm exhibited an on-state drain current density as high as approximately 270 mA/mm and an off-state breakdown voltage of approximately 1 kV, which corresponds to an off-state critical electric field of 166 V/μm. This breakdown field, as a comparison in devices without field-plate electrodes, reaches approximately four-fold higher than that for conventional GaN-channel HFETs and was considered quite reasonable as an Al0.36Ga0.64N-channel transistor. It was also confirmed that the devices adopting the dual AlN/AlGaInN barrier layer showed approximately one order of magnitude smaller gate leakage currents than those for devices without the top AlN barrier layer.

Study of Porous Silica Based Films as Low-k Dielectric Material and their Interface with Copper Metallization

2002 ◽  
Vol 716 ◽  
Author(s):  
Ilanit Fisher ◽  
Wayne D. Kaplan ◽  
Moshe Eizenberg ◽  
Michael Nault ◽  
Timothy Weidman
Keyword(s):  
Integrated Circuits ◽  
Dielectric Material ◽  
Hydrogen Plasma ◽  
Porous Silica ◽  
Film Deposition ◽  
Copper Metallization ◽  
High Porosity ◽  
Tem Analysis ◽  
Chip Technology ◽  
Low K

AbstractThe success of future gigascale integrated circuits (IC) chip technology depends critically upon the reduction of the interconnects RC delay time. This calls for the development of new low dielectric constant (low-k) insulators, and for work on their integration with lower resistivity copper metallization.A porous silica based film prepared by surfactant templated self-assembly spin-on deposition (SOD) is an attractive candidate as a low-k material. In this research we have studied the structure, chemical composition and bonding of the film and its interface with copper metallization. The decomposition and vaporization of the surfactant in the last step of film deposition resulted in a film with an amorphous structure, as determined by XRD and TEM analysis. Its high porosity (35-58%) was confirmed by XRR and RBS measurements. XPS analysis of the Si2p transition indicated three types of bonding: Si-O, O-Si-C and Si-C. The bonding characteristics were also investigated by FTIR analysis. The effect of a hydrogen plasma post-treatment process on the film topography and bonding was determined by AFM and XPS, respectively. It was found that direct H2 plasma exposure significantly affected the surface roughness of the film and type of chemical bonding. The structure and properties of various PECVD deposited capping layers were also studied, as was the interface between the porous dielectric and Ta, TaxN and Cu (PVD deposited films) after annealing at 200-700°C in vacuum environment for 30 min. At temperatures up to 500°C, no significant diffusion of Cu or Ta into the porous film was detected, as determined by RBS. No copper penetration was detected up to 700°C, according to AES and SIMS analysis. However, at 700°C copper dewetting occurred when it was deposited directly on the porous silica based film.

Advanced Die Saw Technology for WLCSP Reliability Enhancement

2019 ◽  
Vol 2019 (1) ◽  
pp. 000323-000326
Author(s):  
Ching Chia Chen ◽  
Yu-Po Wang ◽  
Jensen Tsai ◽  
Hsin Long Chen
Keyword(s):  
Plasma Etching ◽  
Dielectric Material ◽  
Side Wall ◽  
Bending Test ◽  
Process Time ◽  
Portable Devices ◽  
Coating Materials ◽  
Reliability Enhancement ◽  
Surrounding Areas ◽  
Low K

Abstract As consumer and portable devices get thinner and more functionality. Chips which are made by less than 28 nm node wafer with extreme Low-k (ELK) inter metal dielectric material is a trend in order to contain more transistors and to lower power consumption. However, side wall crack (SWC) for WLCSP is one of the major challenges since ELK layer getting brittle. Laser grooving is applied to remove metal before blade saw, but the high temperature during laser grooving usually easily generates HAZ (heat-affected zone) which can induce stress concentration and lower chip strength. The laser ablation also leaves metal-silicon residue (or recast) from the re-deposition of silicon to the groove and surrounding areas. Therefore, SWC (sidewall crack) is a huge potential risk waiting to happen after pick and place, during shipment and during SMT process. In the industry, HAZ size and SWC rate could be reduced by adjusting process parameters, or by exploring new alternatives to eliminate HAZ and silicon recast is one of driving factors of this paper. In this study, plasma etching was applied as surface treatment on the scribe line after laser grooving process with ELK wafer. Plasma could etch HAZ and recast area and expected to increase chip strength and reduce SWC rate. Plasma applied with various process time and power, and different types of mask coating materials were studied. Different plasma gases and effectiveness will be discussed. Conventional blade dicing process will be compared to different plasma etching conditions for mechanical properties of die using 3-point bending test to check die strength, and SEM and OM to verify quality of sidewall of the die. Finally drop test was performed to confirm the reliability enhancement.

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

2007 ◽  
Vol 129 (4) ◽  
pp. 460-468 ◽  
Author(s):  
Karan Kacker ◽  
Thomas Sokol ◽  
Wansuk Yun ◽  
Madhavan Swaminathan ◽  
Suresh K. Sitaraman
Keyword(s):  
Flip Chip ◽  
Dielectric Material ◽  
Coefficient Of Thermal Expansion ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Integrative Approach ◽  
Wafer Level ◽  
Target Values ◽  
Low K

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

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