Short-Channel Effect Suppression In Silicon Carbide Power Mesfets

2000 ◽  
Vol 640 ◽  
Author(s):  
A. Konstantinov ◽  
A-M. Saroukhan ◽  
S. Karlsson ◽  
C. Harris ◽  
A. Litwin
Keyword(s):  
Silicon Carbide ◽  
The Other ◽  
Gate Length ◽  
Short Channel Effects ◽  
Short Channel ◽  
Short Channel Effect ◽  
Turn On ◽  
Channel Effect ◽  
Blocking Voltage ◽  
Channel Effects

ABSTRACTWe demonstrate that the performance of silicon carbide MESFETs is largely determined by short-channel effects. Parasitic bipolar transistor turn-on limits the operation voltage to a small fraction of the theoretically expected value for an ideal device. Tradeoffs are shown to exist between optimum gate length and on-state current on one hand, and the maximum blocking voltage on the other hand. Composite p-buffers with an elevated doping in the vicinity of the active layer considerably increase the operation voltage. Silicon carbide MESFETs utilizing composite buffers are reported.

Germanium & Carbon Co-implantation for Enhanced Short Channel Effect Control in PMOS Devices

2006 ◽  
Vol 912 ◽  
Author(s):  
Benjamin Dumont ◽  
Arnaud Pouydebasque ◽  
Bartek Pawlak ◽  
Benjamin Oudet ◽  
Dominique Delille ◽  
...  
Keyword(s):  
Short Channel Effects ◽  
Short Channel ◽  
Short Channel Effect ◽  
Drive Current ◽  
Enhanced Diffusion ◽  
Channel Effect ◽  
Interstitial Defects ◽  
Shallow Junctions ◽  
Channel Effects ◽  
Large Improvement

AbstractThis work demonstrates the efficiency of a Germanium and Carbon co-implantation that suppresses the Boron Transient Enhanced Diffusion, enhances Boron activation and enables large improvement of Short Channel Effects in PMOS devices while maintaining drive current performances. We present here 65/45nm node devices on conventional bulk substrates featuring Germanium and Carbon engineered shallow junctions that enable to reduce the Drain Induced Barrier Lowering compared to devices implanted only with Boron. This improvement is attributed to the suppression of Boron channelling with Ge pre-amorphization (PAI), and to the reduction of Boron TED due to the trapping of interstitial defects by Carbon with Germanium PAI.

Suppression of Short-Channel Effects in 4H-SiC Trench MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 613-616
Author(s):  
Tomoyasu Ishii ◽  
Shinichiro Kuroki ◽  
Hiroshi Sezaki ◽  
Seiji Ishikawa ◽  
Tomonori Maeda ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Threshold Voltage ◽  
High Frequency ◽  
Short Channel Effects ◽  
Short Channel ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Channel Effects ◽  
Trench Structure ◽  
High Frequency Operation

Submicron 4H-SiC MOSFETs are attractive for high frequency operation of 4H-SiC integrated circuits. However, the short channel effects, such as threshold voltage lowering, would be induced at the short-channel devices. In this work, short channel effects were investigated with planar and trench 4H-SiC MOSFETs, and the suppression of the short channel effect with the trench structure was achieved.

Short gate length AlGaN/GaN HEMTs

2000 ◽  
Vol 622 ◽  
Author(s):  
O. Breitschädel ◽  
L. Kley ◽  
H. Gräbeldinger ◽  
B. Kuhn ◽  
F. Scholz ◽  
...  
Keyword(s):  
High Frequency ◽  
Device Performance ◽  
Gate Length ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Gan Hemts ◽  
Output Characteristics ◽  
Frequency Behavior ◽  
Nm Range

ABSTRACTWe report on our progress on the fabrication of AlGaN/GaN HEMTs with extremely short gate length. AlGaN/GaN HEMTs with different gate length from 6 νm down to 60nm were fabricated to investigate DC- and high frequency behavior as well as short channel effects. We have found that the transistors with gates in the 100 nm range can be improved in the device performance with respect to transconductance and high frequency but shows also short channel effects as the loss of saturation in the output characteristics and a strong dependency of the threshold voltage on the gate length.

50nm Gate-Length Hydrogen Terminated Diamond Field Effect Transistors – Characterization and Inspection of Operation.

2011 ◽  
Vol 1282 ◽  
Author(s):  
David A. J. Moran ◽  
Donald A. MacLaren ◽  
Samuele Porro ◽  
Richard Hill ◽  
Helen McLelland ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Gate Length ◽  
Short Channel Effects ◽  
Short Channel ◽  
Transmission Electron ◽  
Channel Effects ◽  
Physical And Chemical ◽  
Electron Energy Loss

ABSTRACTHydrogen terminated diamond field effect transistors (FET) of 50nm gate length have been fabricated, their DC operation characterised and their physical and chemical structure inspected by Transmission Electron Microscopy (TEM) and Electron Energy Loss Spectroscopy (EELS). DC characterisation of devices demonstrated pinch-off of the source-drain current can be maintained by the 50nm gate under low bias conditions. At larger bias, off-state output conductance increases, demonstrating most likely the onset of short-channel effects at this reduced gate length.

scholarly journals Effect of Oxide Thickness on GaN-based Double Gate MOSFETs

2020 ◽  
Vol 16 (2) ◽  
Author(s):  
Safayet Ahmed ◽  
Md. Tanvir Hasan
Keyword(s):  
Oxide Thickness ◽  
Device Performance ◽  
Gate Length ◽  
Double Gate ◽  
Short Channel Effects ◽  
Subthreshold Slope ◽  
Short Channel ◽  
Power Switching ◽  
Switching Device ◽  
Channel Effects

The effect of oxide thickness (EOT) on GaN-based double gate (DG) MOSFETs have been explored for low power switching device. The gate length (LG) of 8 nm with 4 nm underlap is considered. The device is turned off and on for gate voltage (VGS) of 0 V and 1 V, respectively. The effective oxide thickness (EOT) is varied from 1 nm to 0.5 nm and the device performance is evaluated. For EOT = 0.5 nm, the OFF-state current (IOFF), subthreshold slope (SS) and drain induced barrier lowering (DIBL) are obtained 2.97×10-8 A/μm, 69.67 mV/dec and 21.753 mV/V, respectively. These results indicate that, it is possible to minimize short channel effects (SCEs) by using smaller value of EOT.

0.5- mu m gate length self-aligned gate MODFET with reduced short-channel effects

1988 ◽  
Vol 35 (12) ◽  
pp. 2448-2449
Author(s):  
C.J. Han ◽  
D. Grider ◽  
K. Newstrom ◽  
P. Joslyn ◽  
A. Fraasch ◽  
...  
Keyword(s):  
Gate Length ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects

Suppression of Short Channel Effects in Ferroelectric Si Junctionless Transistors with 8 nm Gate Length Defined by Helium Ion Beam Lithography

2021 ◽  
Author(s):  
Teng Jan Chang ◽  
Ting-Yun Wang ◽  
Chin-I Wang ◽  
Zheng-da Huang ◽  
Yu-Sen Jiang ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Ion Beam ◽  
Gate Length ◽  
Short Channel Effects ◽  
Short Channel ◽  
Ion Beam Lithography ◽  
Helium Ion ◽  
Channel Effects ◽  
Junctionless Transistors ◽  
First Time

Performance enhancements of Si junctionless transistors (JLTs) with a short gate length (LG) of only ~8 nm by a pronounced ferroelectric (FE) gate dielectric are demonstrated for the first time....

The Carbon Co-implant with Spike RTA Solution for Phosphorus Extension

2006 ◽  
Vol 912 ◽  
Author(s):  
Bartek Pawlak ◽  
Ray Duffy ◽  
Emmanuel Augendre ◽  
Simone Severi ◽  
Tom Janssens ◽  
...  
Keyword(s):  
Rapid Thermal Annealing ◽  
Successful Implementation ◽  
Gate Length ◽  
Short Channel Effects ◽  
Mos Transistors ◽  
Short Channel ◽  
Mos Devices ◽  
Channel Effects ◽  
20 Nm ◽  
The Impact

AbstractAs extensions have been up till now always used in N-MOS transistors with an activation anneal. Here, we show that also alternative doping by P can result in junction extensions that are extremely abrupt and shallow thus suitable for upcoming transistor technologies. P extensions are manufactured by amorphization, carbon co-implantation and conventional rapid thermal annealing (RTA). The impact of Si interstitials (Sii) flux suppression on the formation of P junction extensions during RTA is demonstrated. We have concluded that optimization of implants followed by RTA spike offers excellent extensions with depth Xj = 20 nm (taken at 5 × 1018 at./cm3), abruptness 3 nm/dec. and Rs = 326 Ω. Successful implementation of these junctions is straightforward for N-MOS devices with 30 nm gate length and results in an improved short channel effects with respect to the As reference.

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