Evaluation of Candidate Metals for Dual-Metal Gate CMOS with HfO2 Gate Dielectric

2002 ◽  
Vol 716 ◽  
Author(s):  
S.B. Samavedam ◽  
J.K. Schaeffer ◽  
D.C. Gilmer ◽  
V. Dhandapani ◽  
P.J. Tobin ◽  
...  

AbstractAs the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high K) material. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled down to 10 Å equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other problems like boron penetration and enhanced gate resistance that will have increased focus as the polysilicon gate thickness is reduced. Extensive simulations have shown that the optimal gate work-functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-MOSFETs (p-MOSFETs). This study summarizes the evaluations of TiN, TaSiN, WN, TaN, TaSi, Ir and IrO2 as candidate metals for dual-metal gate CMOS using HfO2 as the gate dielectric. The gate work-function was determined by fabricating MOS capacitors with varying dielectric thicknesses and different post-gate anneals. The metal-dielectric compatibility and thermal stability was studied by annealing the stacks at different temperatures. The gate stacks were characterized using TEM, SIMS and X-ray diffraction. Based on workfunctions and thermal stability, TaSiN and TaN show most promise as metal electrodes for HfO2 n-MOSFETs.

2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Wu-Te Weng ◽  
Yao-Jen Lee ◽  
Horng-Chih Lin ◽  
Tiao-Yuan Huang

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.


2000 ◽  
Vol 611 ◽  
Author(s):  
Yanjun Ma ◽  
Yoshi Ono

ABSTRACTZrO2 films are investigated as an alternative to SiO2 gate dielectric below 1.5nm. A maximum accumulation capacitance ∼35 fF/μm2 with a leakage current of less than 0.1 A/cm2 has been achieved for a 3 nm Zr-O film, suggesting that ZrO2 can be scaled to below an equivalent oxide thickness of 0.5 nm. Al and Si doping is also investigated to reduce leakage currents and to increase the crystallization temperature of the film. Submicron MOSFETs with TiN or Pt gate electrodes have been fabricated with these gate dielectrics with excellent characteristics, demonstrating the feasibility of CMOS process integration. In particular, Pt damascene gate PMOS is shown to have the proper threshold voltage for dual metal gate CMOS application.


2008 ◽  
Vol 2008 ◽  
pp. 1-5 ◽  
Author(s):  
A. Bouazra ◽  
S. Abdi-Ben Nasrallah ◽  
M. Said ◽  
A. Poncet

With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10), Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V) and C(V) characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width) at the Al2O3/SiO2 interface is also discussed.


2002 ◽  
Vol 81 (22) ◽  
pp. 4192-4194 ◽  
Author(s):  
Tae-Ho Cha ◽  
Dae-Gyu Park ◽  
Tae-Kyun Kim ◽  
Se-Aug Jang ◽  
In-Seok Yeo ◽  
...  

1999 ◽  
Vol 567 ◽  
Author(s):  
B. Claflin ◽  
K. Flock ◽  
G. Lucovsky

ABSTRACTSeveral metal and conducting metal nitride candidates were investigated for alternative gate electrode applications in future complimentary metal-oxide-semiconductor (CMOS) devices. High frequency capacitance-voltage (CV) measurements were performed on n-MOS and p-MOS capacitors with Al, Ta, TaN, TIN, or W2N gates and ultra-thin SiO2/Si3N4 dielectric stacks. The work functions of Al and Ta were close to the conduction band of Si as expected while all the metal nitrides had work functions slightly above mid-gap. The thermal stability of the metal nitrides and the metal/dielectric interfaces was studied by Auger electron spectroscopy (AES) following rapid thermal annealing (RTA). Integration requirements for dual metal gate electrodes in future CMOS devices are discussed.


2003 ◽  
Vol 786 ◽  
Author(s):  
F. Fillot ◽  
S. Maîtrejean ◽  
T. Farjot ◽  
B. Guillaumot ◽  
B. Chenevier ◽  
...  

ABSTRACTAs gate oxide thickness decreases, the capacitance associated with the depleted layer in polysilicon gate becomes significant, making it necessary to consider alternative gate electrodes. Titanium nitride (TiN) films elaborated with TiCl4 precursor is widely studied as metal gate in semi-conductor technology. In this work, a study of TiN metal gate deposited by MOCVD using TDMAT (Tetrakisdimethylamino titanium) precursor is proposed. N2, H2 plasma application and SiH4 treatment after TiN thin film growth modify composition and microstructure. Consequently, they alter the physical properties of films. Such treatments may be a way to modulate work function and thus to control threshold voltage.Metallic layers were deposited in a chamber using a commercial 8 inch wafer deposition tool. In this study, structural and compositional properties of TiN were correlated with work function measurements. Firstly, the composition evolution (carbon content) was studied by AES and SIMS as a function of plasma and SiH4 treatments; XRD gave details on the microstructure. Secondly, MOS structures were processed on uniformly p-type doped wafers. C-V curves of capacitors were used to estimate the flat band voltage (VFB) and gave access to the work function, the effect of oxide fixed charges and the density of interface states. It is shown that as-deposited amorphous films exhibit a work function of 4.4 eV. Exposure to SiH4 is shown to increase this work function of about 150 meV. Thin films properties are not impacted by anneal treatments. Work function stability was tested at 425 °C, 900 °C and 1050 °C. Thermodynamic compatibility with gate oxide was verified thanks to experimental results and calculations.


2001 ◽  
Vol 670 ◽  
Author(s):  
Hyungsuk Jung ◽  
Hyundoek Yang ◽  
Kiju Im ◽  
Hyunsang Hwang

ABSTRACTThis letter describes a unique process for the preparation of high quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional native silicon oxide and oxynitride as an interfacial layer, tantalum oxynitride (TaOxNy) MOS capacitors using zirconium silicate (ZrSixOy) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm TaOxNy/ZrSixOy stack structure by auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The estimated dielectric constant of TaOxNy and ZrSixOywere approximately 67 and 7, respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.


2008 ◽  
Vol 47 (4) ◽  
pp. 2428-2432 ◽  
Author(s):  
Takashi Matsukawa ◽  
Yongxun Liu ◽  
Kazuhiko Endo ◽  
Meishoku Masahara ◽  
Yuki Ishikawa ◽  
...  

2002 ◽  
Vol 716 ◽  
Author(s):  
Krishna Kumar Bhuwalka ◽  
Nihar R. Mohapatra ◽  
Siva G. Narendra ◽  
V Ramgopal Rao

AbstractIt has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric.


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