High-k Dielectrics and Dual Metal Gates: Integration Issues for New CMOS Materials

1999 ◽  
Vol 567 ◽  
Author(s):  
B. Claflin ◽  
K. Flock ◽  
G. Lucovsky
Keyword(s):  
Oxide Semiconductor ◽  
Metal Nitrides ◽  
Mos Capacitors ◽  
Gate Electrodes ◽  
Metal Gates ◽  
High K ◽  
Dielectric Interfaces ◽  
Work Functions ◽  
Dual Metal ◽  
Cv Measurements

ABSTRACTSeveral metal and conducting metal nitride candidates were investigated for alternative gate electrode applications in future complimentary metal-oxide-semiconductor (CMOS) devices. High frequency capacitance-voltage (CV) measurements were performed on n-MOS and p-MOS capacitors with Al, Ta, TaN, TIN, or W2N gates and ultra-thin SiO2/Si3N4 dielectric stacks. The work functions of Al and Ta were close to the conduction band of Si as expected while all the metal nitrides had work functions slightly above mid-gap. The thermal stability of the metal nitrides and the metal/dielectric interfaces was studied by Auger electron spectroscopy (AES) following rapid thermal annealing (RTA). Integration requirements for dual metal gate electrodes in future CMOS devices are discussed.

scholarly journals Leakage Current Conduction Mechanism of Au-Pt-Ti/ HfO2-Al2O3/n-InAlAs Metal-Oxide-Semiconductor Capacitor under Reverse-Biased Condition

Coatings ◽  
2019 ◽  
Vol 9 (11) ◽  
pp. 720
Author(s):  
He Guan ◽  
Shaoxi Wang
Keyword(s):  
Metal Oxide ◽  
Leakage Current ◽  
Photoelectron Spectroscopy ◽  
Metal Oxide Semiconductor ◽  
Schottky Emission ◽  
Oxide Semiconductor ◽  
Optimized Design ◽  
Mos Capacitors ◽  
Leakage Mechanism ◽  
High K

Au-Pt-Ti/high-k/n-InAlAs metal-oxide-semiconductor (MOS) capacitors with HfO2-Al2O3 laminated dielectric were fabricated. We found that a Schottky emission leakage mechanism dominates the low bias conditions and Fowler–Nordheim tunneling became the main leakage mechanism at high fields with reverse biased condition. The sample with HfO2 (4 m)/Al2O3 (8 nm) laminated dielectric shows a high barrier height ϕB of 1.66 eV at 30 °C which was extracted from the Schottky emission mechanism, and this can be explained by fewer In–O and As–O states on the interface, as detected by the X-ray photoelectron spectroscopy test. These effects result in HfO2 (4 m)/Al2O3 (8 nm)/n-InAlAs MOS-capacitors presenting a low leakage current density of below 1.8 × 10−7 A/cm2 from −3 to 0 V at 30 °C. It is demonstrated that the HfO2/Al2O3 laminated dielectric with a thicker Al2O3 film of 8 nm is an optimized design to be the high-k dielectric used in Au-Pt-Ti/HfO2-Al2O3/InAlAs MOS capacitor applications.

Progress in Epitaxial Oxides on Semiconductors

2002 ◽  
Vol 747 ◽  
Author(s):  
Z. Yu ◽  
Y. Liang ◽  
H. Li ◽  
J. Curless ◽  
C. Overgaard ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Surface Preparation ◽  
Future Generation ◽  
Silicon On Insulator ◽  
Buffer Layers ◽  
Oxide Semiconductor ◽  
Perovskite Oxide ◽  
High Quality ◽  
Mos Capacitors ◽  
High K

ABSTRACTIn this paper, we review the recent progress in the area of epitaxial oxides on semiconductors at Motorola Labs. Critical issues such as surface preparation, initial nucleation and growth behaviors of SrTiO3 (STO) thin film epitaxy on Si(001) are addressed. Using a systematic approach, high-quality epitaxial STO films are successfully grown on semiconductor substrates such as Si, silicon-on-insulator (SOI) and Ge. Amorphous interfacial layer between the epitaxial STO and the semiconductor can be eliminated or tailored by controlling oxide growth process and parameters. STO-based metal-oxide-semiconductor (MOS) capacitors and transistors are fabricated and tested, in order to explore the potential of STO as high-k gate dielectrics for future generation CMOS transistor technology. In addition, high-quality STO epitaxial films are utilized as thin buffer layers for fabricating integrated oxide heterostructures on semiconductors. Various perovskite oxide films such as SrZrO3, LaAlO3 and Pb(Zr,Ti)O3 are deposited epitaxially on STO-buffered Si(001) for potential high-k gate dielectrics and surface-acoustic-wave (SAW) device applications.

Investigation of the Growth and Chemical Stability of Composite Metal Gates on Ultra-thin Gate Dielectrics

1998 ◽  
Vol 532 ◽  
Author(s):  
B. Claflin ◽  
M. Binger ◽  
G. Lucovsky ◽  
H.-Y. Yang
Keyword(s):  
Chemical Stability ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Mos Capacitors ◽  
Metal Gates ◽  
Bulk Film ◽  
Chemical Vapor Deposited ◽  
Capacitance Voltage ◽  
Dielectric Interfaces ◽  
On Line

ABSTRACTThe growth of reactively sputtered TiNx and WNx compound metal films on ultra-thin, remote plasma enhanced chemical vapor deposited SiO2 and SiO2/Si3N4 (ON) stack dielectrics is investigated from initial interface formation to bulk film by interrupted growth and on-line Auger electron spectroscopy (AES). Growth of both metals occurs uniformly without a seed layer on both dielectrics. The chemical stability of these metal/dielectric interfaces is studied by sequential on-line rapid thermal annealing treatments up to 850 °C and AES. TiNx reacts with SiO2 above 850 °C but the addition of a Si3N4 dielectric top-layer makes the TiNx/ON interface chemically stable at 850 °C. WNx/SiO2 and WNx/Si3N4 interfaces are both stable below 650 °C. MOS capacitors using TiNx or WNx metal gates and thermal SiO2 gate dielectrics exhibit excellent capacitance-voltage characteristics. The work function for TiNx lies near midgap in Si while for WNx it lies closer to the valence band.

Impact of Galvanic Corrosion on Metal Gate Stacks

2009 ◽  
Vol 145-146 ◽  
pp. 215-218
Author(s):  
Masayuki Wada ◽  
Sylvain Garaud ◽  
I. Ferain ◽  
Nadine Collaert ◽  
Kenichi Sano ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Galvanic Corrosion ◽  
Gate Stacks ◽  
Metal Gate Electrodes ◽  
Metal Gate ◽  
Fermi Level Pinning ◽  
Gate Electrodes ◽  
High K ◽  
Work Functions

High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.

Sign in / Sign up

Export Citation Format

Share Document