scholarly journals CENSORSHIP OF LEAKAGE PARAMETERS OF A FINFET BASED SCHMITT TRIGGER AT NANO-METER REGIME

2020 ◽  
Vol 8 (2) ◽  
pp. 01-05
Author(s):  
Vishwas Mishra ◽  
Abhishek Kumar ◽  
Shobhit Tyagi ◽  
Neha Verma ◽  
Divya Mishra
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Past Research ◽  
Schmitt Trigger ◽  
Short Channel ◽  
Power Efficient ◽  
Channel Effects ◽  
Potential Applications ◽  
Trigger Circuit ◽  
Full Swing

Purpose: Recently FinFET technology has gained a lot of attention because of its superior fabrication process that is very similar to the fabrication of a conventional transistor. FinFETs unique feature as well as the potential applications make it a strong contender for the low power chip designs. Research is in full swing to use FinFET in analog circuits like Schmitt trigger, sensors, OPAMP and digital logic. The realization of the FinFET based circuits predicts that it is possible to broaden the concept of Moore’s law without unstoppable scaling of CMOS devices. Methodology: This work is carried out on the Candence Simulation tool. After the simulation, all these parameters have been compared with previous published 4T Schmitt trigger at 45nm with this design and found that they are in close vicinity. Main Findings: By combining the superior flexibility and reduced short channel effects (SCEs) of FinFET devices offers a promising approach to implement highly integrated, power-efficient Schmitt Trigger circuit for low power digital applications. Schmitt trigger is a device capable of removing unwanted noise from the input and prevent the other operations from this unwanted noise and improve the performance of the device. Implications: This study is discussing and performs a comparative analysis of different leakage parameters of a FinFET based Schmitt Trigger with previous 4T Schmitt Trigger at 45nm. The novelty of Study: Size, power, speed, Cost etc. are important factors for designing any new circuits in the field of Electronics. Various eminent researchers have been making efforts for this. This paper makes some effort to discuss about past research and design a new circuit where the value of delay, leakage power and dynamic power reduces when compared to previously published circuits.

CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

2006 ◽  
Vol 16 (01) ◽  
pp. 193-219 ◽  
Author(s):  
S. DELEONIBUS ◽  
B. de SALVO ◽  
T. ERNST ◽  
O. FAYNOT ◽  
T. POIROUX ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Short Channel Effects ◽  
Short Channel ◽  
Trade Offs ◽  
Future System ◽  
The Future ◽  
Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs

2019 ◽  
Vol E102.C (6) ◽  
pp. 487-494 ◽  
Author(s):  
Arnab MUKHOPADHYAY ◽  
Tapas Kumar MAITI ◽  
Sandip BHATTACHARYA ◽  
Takahiro IIZUKA ◽  
Hideyuki KIKUCHIHARA ◽  
...  
Keyword(s):  
Short Channel Effects ◽  
Short Channel ◽  
Power Efficient ◽  
Channel Effects

Low power Schmitt trigger circuit

2002 ◽  
Vol 38 (18) ◽  
pp. 1009 ◽  
Author(s):  
S.F. Al-Sarawi
Keyword(s):  
Low Power ◽  
Schmitt Trigger ◽  
Trigger Circuit ◽  
Schmitt Trigger Circuit

Advances in AlGaN/GaN/SiC Microwave Devices

2007 ◽  
Vol 556-557 ◽  
pp. 1017-1022 ◽  
Author(s):  
Michael J. Uren ◽  
Martin Kuball
Keyword(s):  
Field Effect Transistors ◽  
Deep Level ◽  
Substrate Material ◽  
Microwave Devices ◽  
Short Channel Effects ◽  
Short Channel ◽  
Active Device ◽  
Efficient Operation ◽  
Power Efficient ◽  
Channel Effects

Recent work on the thermal and electrical challenges in realizing AlGaN/GaN microwave heterojunction field effect transistors grown on SiC substrates is discussed. Raman thermography has been used to directly measure the self-heating induced lattice temperature rise with dramatically improved resolution and accuracy compared to traditional infrared techniques. It is demonstrated that defects in the SiC substrate can influence the temperature distribution within the active device with potential consequences for reliability. Microwave devices require an insulating GaN substrate material for device isolation. It is shown that the net deep level acceptor concentration has to be accurately controlled to suppress short-channel effects and to achieve radio frequency power efficient operation.

Analytical Modeling for Short Channel SOI-MOSFET and to Study its Performance

2011 ◽  
Vol 110-116 ◽  
pp. 5150-5154
Author(s):  
K. Senthil Kumar ◽  
Saptarsi Ghosh ◽  
Anup Sarkar ◽  
S. Bhattacharya ◽  
Subir Kumar Sarkar
Keyword(s):  
Low Power ◽  
Threshold Voltage ◽  
Cmos Technology ◽  
Current Drive ◽  
Silicon On Insulator ◽  
Short Channel Effects ◽  
Short Channel ◽  
Soi Mosfet ◽  
Silicon Bulk ◽  
Channel Effects

With the emergence of mobile computing and communication, low power device design and implementation have got a significant role to play in VLSI circuit design. Conventional silicon (bulk CMOS) technology couldn‘t overcome the fundamental physical limitations belonging to sub-micro or nanometer region which leads to alternative device technology like Silicon-on-Insulator (SOI) technology. In a fully-depleted FDSOI structure the electrostatic coupling of channel with source/drain and substrate through the buried layer (BL) is reduced. This allows in turn to reduce the minimal channel length of transistors or to relax the requirements on Si film thickness. A generalized compact threshold voltage model for SOI-MOSFET is developed by solving 2-D Poisson‘s equation in the channel region and analytical expressions are also developed for the same. The performance of the device is evaluated after incorporating the short channel effects. It is observed that in SOI, presence of the oxide layer resists the short channel effects and reduces device anomalies such as substrate leakage by a great factor than bulk-MOS. The threshold voltage and current drive make SOI the ultimate candidate for low power application. Thus SOI-MOSFET technology could very well be the solution for further ultra scale integration of devices and improvised performance.

scholarly journals Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs

2021 ◽  
Vol 7 (1) ◽  
pp. 18-29
Author(s):  
Vinod Pralhad Tayade ◽  
Swapnil Laxman Lahudkar
Keyword(s):  
Low Power ◽  
Field Effect ◽  
High Speed ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
20 Nm ◽  
Graphene Material

In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

scholarly journals Design of Low Power Less Leakage Quarternary Adder Using CMOS

2021 ◽  
pp. 110-121
Author(s):  
M. Sutha ◽  
Dr. R. Nirmala ◽  
Dr. E. Kamalavathi
Keyword(s):  
Low Power ◽  
Impact Ionization ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Surface Scattering ◽  
Short Channel Effects ◽  
Short Channel ◽  
Mos Devices ◽  
Channel Effects ◽  
Quaternary Adder

In VLSI, design and implementation of circuits with MOS devices and binary logic are quite usual. The Main Objective is to design a low power and minimum leakage Quaternary adder. The VLSI field consists of Multi-valued logic (MVL) such as ternary and Quaternary Logic (QTL). The Failures such as Short Channel Effects (SCE) Impact-ionization and surface scattering are in normalized aspects. The Quaternary radix on MVL (multi-valued logic) monitors and reduces the area. The Quaternary (four-valued) logic converts the quaternary signals and binary signals produced by the by the existing binary circuits. The Proposed is carried out with LTSPICE tool and CMOS technology.

scholarly journals High-k Dielectric Double Gate Junctionless (DG-JL) MOSFET for Ultra Low Power Applications- Analytical Model

2021 ◽  
Author(s):  
Prashant Kumar ◽  
Munish Vashishath ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Analytical Model ◽  
Threshold Voltage ◽  
Figure Of Merit ◽  
Double Gate ◽  
Short Channel ◽  
Ultra Low Power ◽  
High K ◽  
Channel Effects ◽  
High K Dielectric

Abstract This paper describes the impression of low-k/high-k dielectric on the performance of Double Gate Junction less (DG-JL) MOSFET. An analytical model of the threshold voltage of DG-JLFET has been presented. Poisson’s equation is solved using the parabolic approximation to find out the threshold voltage. The effect of high-k on various performance parameters of N-type DG-JLFET is explored. The comparative analysis has been carried out between conventional gate oxide, multi oxide and high-k oxide in terms of Drain Induced Barrier Lowering (DIBL), threshold voltage, figure of merit (ION/IOFF) and sub-threshold slope (SS). The high-k oxide has shown superlative performance as compared to others. The results are further analyzed for various device structures. The DG-JLFET with HfO2 exhibits excellent attainment by mitigating the Short Channel Effects (SCEs). The significant reduction in off current makes the device suitable for ultra-low power applications. There is a 61.9 % and 34.29% improvement in the figure of merit and sub-threshold slope in the proposed device as compared to other devices. The simulation of DG-JLFET is carried out using the Silvaco TCAD tool.

Effect of strain in silicon nanotube FET devices for low power applications

2019 ◽  
Vol 85 (1) ◽  
pp. 10101 ◽  
Author(s):  
Avtar Singh ◽  
Chandan Kumar Pandey ◽  
Saurabh Chaudhury ◽  
Chandan Kumar Sarkar
Keyword(s):  
Low Power ◽  
Silicon Germanium ◽  
High Speed ◽  
Axial Strain ◽  
Three Dimensional ◽  
Short Channel ◽  
Strained Si ◽  
Channel Effects ◽  
Germanium Layer ◽  
Silicon Nanotube

In this paper, we have presented an analysis on the performance of a strained silicon channel in silicon nanotube FET (Si-NTFET) device. Si-NTFET devices have tube-shaped channel region and because of this conduction in the channel can be controlled in two ways from outside the tube and from inside (from hollow side) the tube which results in better control over the short channel effects (SCEs). Bi-axial strain induced into the device by the inclusion of silicon-–germanium layer in between the channel. Three-dimensional simulations of the structure are carried out using ATLAS TCAD simulator and the model is calibrated with respect to previously published experimental data. The transfer characteristics, drain induced barrier lowering (DIBL), threshold voltage, Ion and Ioff, subthreshold swing of the Si-NTFET and strained Si-NTFET devices are investigated. It is seen that in strained Si-NTFET, the drive capability and inversion charge density is much higher compared to that of Si-NTFET. Evaluation of electrical performances confirms that the DIBL and other SCEs are either reduced or remains the same. However, the use of strained Si-NTFET is more suited for high speed and low power applications.

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