scholarly journals Analytical Breakdown Voltage Model for Partial SOI-LDMOS Transistor with Buried Oxide Step Structure

2021 ◽  
Author(s):  
Jagamohan Sahoo ◽  
Rajat Mahapatra
Keyword(s):  
Electric Field ◽  
Analytical Model ◽  
Breakdown Voltage ◽  
Point Of View ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Design Parameters ◽  
Drift Region ◽  
Two Dimensional ◽  
The Impact

Abstract We have developed a simple physics-based two-dimensional analytical Off-state breakdown voltage model of a PBOSS Silicon-On-Insulator Lateral Diffused Metal Oxide Semiconductor (SOI-LDMOS) transistor. The analytical model includes the expressions of surface potential and electric field distributions in the drift region by solving the 2D Poisson’s equation. The electric field at the Si-SiO2 surface is modified by creating additional electric field peaks due to the presence of the PBOSS structure. The uniformly distributed electric field results in improving the breakdown voltage. Further, the breakdown voltage is analytically obtained via critical electric field concept to quantify the breakdown characteristic. The model exploits the impact of the critical device design parameters such as thickness and length of the PBOSS structure, doping, and thickness of the drift region on the surface electric field and the breakdown voltage. The proposed model is verified by the results obtained from ATLAS two dimensional simulations. The analytical model is of the high potential from a physical and mathematical point of view to design high voltage SOI-LDMOS transistors for power switching applications.

A 600V-Class Partial SOI LDMOS with Step-Doped Drift Region

2015 ◽  
Vol 1096 ◽  
pp. 514-519
Author(s):  
Yue Hu ◽  
Hao Wang ◽  
De Wen Wang ◽  
Cai Xia Du ◽  
Miao Miao Ma ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Impurity Atoms ◽  
Surface Field ◽  
Field Peak ◽  
Effect Transistor

A 600V-class lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) in partial silicon-on-insulator (PSOI) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped method induces an electric field peak in the surface of the device, which can reduce the surface field in the device and adjust the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

scholarly journals Impact of Cross-Tie Properties on the Modal Behavior of Cable Networks on Cable-Stayed Bridges

2015 ◽  
Vol 2015 ◽  
pp. 1-14 ◽  
Author(s):  
Javaid Ahmad ◽  
Shaohong Cheng ◽  
Faouzi Ghrib
Keyword(s):  
Analytical Model ◽  
Design Parameters ◽  
Reference Base ◽  
Cable Network ◽  
Cable Networks ◽  
Modal Behavior ◽  
Stiffness And Damping ◽  
Main Cables ◽  
The Impact ◽  
Selection Of

Dynamic behaviour of cable networks is highly dependent on the installation location, stiffness, and damping of cross-ties. Thus, these are the important design parameters for a cable network. While the effects of the former two on the network response have been investigated to some extent in the past, the impact of cross-tie damping has rarely been addressed. To comprehend our knowledge of mechanics associated with cable networks, in the current study, an analytical model of a cable network will be proposed by taking into account both cross-tie stiffness and damping. In addition, the damping property of main cables in the network will also be considered in the formulation. This would allow exploring not only the effectiveness of a cross-tie design on enhancing the in-plane stiffness of a constituted cable network, but also its energy dissipation capacity. The proposed analytical model will be applied to networks with different configurations. The influence of cross-tie stiffness and damping on the modal response of various types of networks will be investigated by using the corresponding undamped rigid cross-tie network as a reference base. Results will provide valuable information on the selection of cross-tie properties to achieve more effective cable vibration control.

Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

2021 ◽  
Author(s):  
Deivakani M ◽  
Sumithra M.G ◽  
Anitha P ◽  
Jenopaul P ◽  
Priyesh P. Gandhi ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Impact Ionization ◽  
Semiconductor Industry ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Physical Models ◽  
Oxide Semiconductor ◽  
Soi Mosfet ◽  
P Type ◽  
Conventional Device

Abstract Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

scholarly journals Electrostatic-Discharge-Immunity Impacts in 300 V nLDMOS by Comprehensive Drift-Region Engineering

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1469 ◽  
Author(s):  
Po-Lin Lin ◽  
Shen-Li Chen ◽  
Sheng-Kai Fan
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
Breakdown Voltage ◽  
Electrostatic Discharge ◽  
Reference Group ◽  
Lateral Diffusion ◽  
Oxide Semiconductor ◽  
Drift Region ◽  
Field Oxide ◽  
Latch Up

Electrostatic discharge (ESD) events are the main factors impacting the reliability of Integrated circuits (ICs); therefore, the ESD immunity level of these ICs is an important index. This paper focuses on comprehensive drift-region engineering for ultra-high-voltage (UHV) circular n-channel lateral diffusion metal-oxide-semiconductor transistor (nLDMOS) devices used to investigate impacts on ESD ability. Under the condition of fixed layout area, there are four kinds of modulation in the drift region. First, by floating a polysilicon stripe above the drift region, the breakdown voltage and secondary breakdown current of this modulation can be increased. Second, adjusting the width of the field-oxide layer in the drift region when the width of the field-oxide layer is 5.8 μm will result in the minimum breakdown voltage (105 V) but the best secondary breakdown current (6.84 A). Third, by adjusting the discrete unit cell and its spacing, the corresponding improved trigger voltage, holding voltage, and secondary breakdown current can be obtained. According to the experimental results, the holding voltage of all devices under test (DUTs) is greater than that of the reference group, so the discrete HV N-Well (HVNW) layer can effectively improve its latch-up immunity. Finally, by embedding different P-Well lengths, the findings suggest that when the embedded P-Well length is 9 μm, it will have the highest ESD ability and latch-up immunity.

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