scholarly journals Current-Induced Crystallisation in Heusler Alloy Films for Memory Potentiation in Neuromorphic Computation

2021 ◽  
Author(s):  
William Frost ◽  
Kelvin Elphick ◽  
Marjan Samiepour ◽  
Atsufumi Hirohata
Keyword(s):  
Heusler Alloy ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Layer Growth ◽  
Oxide Semiconductor ◽  
Layer By Layer ◽  
Alloy Films ◽  
Von Neumann ◽  
Alternative Technologies ◽  
Area Product

Abstract The current information technology has been developed based on von Neumann type computation. In order to sustain the rate of development, it is essential to investigate alternative technologies. Among them, neuromorphic computation has been attracting intensive studies using the current complementary metal oxide semiconductor (CMOS) architecture and beyond in recent years to mimic the functionality and operation of a synapse in a brain. One of the promising synapses is stochastic operation of a magnetic tunnel junction (MTJ). However another important feature of a synapse, memory potentiation, has been overlooked to date. In this study, a giant magnetoresistive (GMR) junction consisting of a half-metallic Heusler alloy is used as an artificial synapse while still achieving a low resistance-area product for low power consumption. Here the Heusler alloy films are grown on a (110) surface to promote layer-by-layer growth to reduce their crystallisation energy, which is comparable with Joule heating induced by a controlled current introduction. The current-induced crystallisation leads to the reduction in the corresponding resistivity, which acts as memory potentiation for an artificial GMR synapse. This offers more realistic neuromorphic computation with higher efficiency.

scholarly journals Current-induced crystallisation in Heusler alloy films for memory potentiation in neuromorphic computation

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
William Frost ◽  
Kelvin Elphick ◽  
Marjan Samiepour ◽  
Atsufumi Hirohata
Keyword(s):  
Heusler Alloy ◽  
Layer Growth ◽  
Layer By Layer ◽  
Half Metallic ◽  
Alloy Films ◽  
Von Neumann ◽  
Alternative Technologies ◽  
Artificial Synapse ◽  
Neumann Type ◽  
Area Product

AbstractThe current information technology has been developed based on von Neumann type computation. In order to sustain the rate of development, it is essential to investigate alternative technologies. In a next-generation computation, an important feature is memory potentiation, which has been overlooked to date. In this study, potentiation functionality is demonstrated in a giant magnetoresistive (GMR) junction consisting of a half-metallic Heusler alloy which can be a candidate of an artificial synapse while still achieving a low resistance-area product for low power consumption. Here the Heusler alloy films are grown on a (110) surface to promote layer-by-layer growth to reduce their crystallisation energy, which is comparable with Joule heating induced by a controlled current introduction. The current-induced crystallisation leads to the reduction in the corresponding resistivity, which acts as memory potentiation for an artificial GMR synaptic junction.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 300-310
Author(s):  
Piyush Tankwal ◽  
Vikas Nehra ◽  
Sanjay Prajapati ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Hall Effect ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Spin Transfer Torque ◽  
Spin Hall Effect ◽  
Oxide Semiconductor ◽  
Content Type

Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

STDP implementation using multi-state spin-orbit torque synapse

2021 ◽  
Author(s):  
Hamdam Ghanatian ◽  
Margherita Ronchini ◽  
Hooman Farkhani ◽  
Farshad Moradi
Keyword(s):  
Learning Algorithm ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Spike Timing ◽  
Oxide Semiconductor ◽  
Spin Orbit ◽  
Ultra Low Power ◽  
Artificial Neural Network Ann ◽  
State Spin

Abstract The abundance of data to be processed calls for new computing paradigms, which could accommodate, and directly map artificial neural network (ANN) architectures at the hardware level. Neuromorphic computing has emerged as a potential solution, proposing the implementation of artificial neurons and synapses on physical substrates. Conventionally, neuromorphic platforms are deployed in complementary metal-oxide–semiconductor (CMOS) technology. However, such implementations still cannot compete with the highly energy-efficient performance of the brain. This calls for novel ultra-low-power nano-scale devices with the possibility of upscaling for the implementation of complex networks. In this paper, a multi-state spin-orbit torque (SOT) synapse based on the three-terminal perpendicular-anisotropy magnetic tunnel junction (P-MTJ) is proposed. In this implementation, P-MTJs use common heavy metals (HMs) but with different cross-section areas, thereby creating multiple states that can be harnessed to implement synapses. The proposed multi-state SOT synapse can solve the state-limited issue of spin-based synapses. Moreover, it is shown that the proposed multi-state SOT synapse can be programmed to reproduce the spike-timing-dependent plasticity (STDP) learning algorithm.

scholarly journals Memristive and CMOS Devices for Neuromorphic Computing

Materials ◽  
2020 ◽  
Vol 13 (1) ◽  
pp. 166 ◽  
Author(s):  
Valerio Milo ◽  
Gerardo Malavena ◽  
Christian Monzio Compagnoni ◽  
Daniele Ielmini
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Low Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Neuromorphic Computing ◽  
Ultra Low Power ◽  
Von Neumann ◽  
Novel Device ◽  
Von Neumann Architecture

Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

scholarly journals Design and analysis of SHE-assisted STT MTJ/CMOS logic gates

2021 ◽  
Author(s):  
Prashanth Barla ◽  
Vinod Kumar Joshi ◽  
Somashekara Bhat
Keyword(s):  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Orbit Interaction ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Oxide Semiconductor ◽  
Metal Materials ◽  
Power Delay Product

AbstractWe have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin–orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.

scholarly journals small

2020 ◽  
Author(s):  
David Moss
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Kerr Nonlinearity ◽  
Oxide Semiconductor ◽  
Layer By Layer ◽  
Large Area ◽  
Low Loss ◽  
Strong Light ◽  
Precise Control ◽  
Light Matter Interaction ◽  
Lift Off

Layered 2D graphene oxide (GO) films are integrated with micro-ringresonators (MRRs) to experimentally demonstrate enhanced nonlinear optics.Both uniformly coated (1−5 layers) and patterned (10−50 layers) GO films areintegrated on complementary-metal-oxide-semiconductor (CMOS)-compatibledoped silica MRRs using a large-area, transfer-free, layer-by-layer GO coatingmethod with precise control of the film thickness. The patterned devices furtheremploy photolithography and lift-off processes to enable precise control of thefilm placement and coating length. Four-wave-mixing (FWM) measurementsfor different pump powers and resonant wavelengths show a significantimprovement in efficiency of 7.6 dB for a uniformly coated device with 1 GOlayer and 10.3 dB for a patterned device with 50 GO layers. The measurementsagree well with theory, with the enhancement in FWM efficiency resultingfrom the high Kerr nonlinearity and low loss of the GO films combined withthe strong light–matter interaction within the MRRs. The dependence of GO’sthird-order nonlinearity on layer number and pump power is also extractedfrom the FWM measurements, revealing interesting physical insights aboutthe evolution of the GO films from 2D monolayers to quasi bulk-like behavior.These results confirm the high nonlinear optical performance of integratedphotonic resonators incorporated with 2D layered GO films.

scholarly journals A Monolithic Stochastic Computing Architecture for Energy and Area Efficient Arithmetic

2022 ◽  
Author(s):  
Harikrishnan Ravichandran ◽  
Yikai Zheng ◽  
Thomas Schranghamer ◽  
Nicholas Trainor ◽  
Joan Redwing ◽  
...  
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Attractive Alternative ◽  
Two Dimensional ◽  
Arithmetic Operations ◽  
Von Neumann ◽  
Stochastic Computing ◽  
Simple Logic

Abstract As the energy and hardware investments necessary for conventional high-precision digital computing continues to explode in the emerging era of artificial intelligence, deep learning, and Big-data [1-4], a change in paradigm that can trade precision for energy and resource efficiency is being sought for many computing applications. Stochastic computing (SC) is an attractive alternative since unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting etc., SC can implement the same using simple logic gates [5, 6]. While it is possible to accelerate SC using traditional silicon complementary metal oxide semiconductor (CMOS) [7, 8] technology, the need for extensive hardware investment to generate stochastic bits (s-bit), the fundamental computing primitive for SC, makes it less attractive. Memristor [9-11] and spin-based devices [12-15] offer natural randomness but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Here we overcome the limitations of existing and emerging technologies and experimentally demonstrate a standalone SC architecture embedded in memory based on two-dimensional (2D) memtransistors. Our monolithic and non-von Neumann SC architecture consumes a miniscule amount of energy < 1 nano Joules for s-bit generation and to perform arithmetic operations and occupy small hardware footprint highlighting the benefits of SC.

Oblique-incidence Reflectivity Difference (OI-RD) and Leed Studies of Adsorption and Growth of Xe on Nb(110)

2003 ◽  
Vol 780 ◽  
Author(s):  
P. Thomas ◽  
E. Nabighian ◽  
M.C. Bartelt ◽  
C.Y. Fong ◽  
X.D. Zhu
Keyword(s):  
Transition Layer ◽  
Layer Growth ◽  
Flow Mode ◽  
Layer By Layer ◽  
Zeroth Order ◽  
Step Flow ◽  
Low Energy Electron Diffraction ◽  
Oriented Film ◽  
Low Energy Electron

AbstractWe studied adsorption, growth and desorption of Xe on Nb(110) using an in-situ obliqueincidence reflectivity difference (OI-RD) technique and low energy electron diffraction (LEED) from 32 K to 100 K. The results show that Xe grows a (111)-oriented film after a transition layer is formed on Nb(110). The transition layer consists of three layers. The first two layers are disordered with Xe-Xe separation significantly larger than the bulk value. The third monolayer forms a close packed (111) structure on top of the tensile-strained double layer and serves as a template for subsequent homoepitaxy. The adsorption of the first and the second layers are zeroth order with sticking coefficient close to one. Growth of the Xe(111) film on the transition layer proceeds in a step flow mode from 54K to 40K. At 40K, an incomplete layer-by-layer growth is observed while below 35K the growth proceeds in a multilayer mode.

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