A New Low Voltage High Performance Dual Port 7-CNT SRAM Cell with Improved Differential Reference Based Sense Amplifier

A new generation of high performance field emission scanning electron microscopes (FSEM) is now commercially available (JEOL 890, Hitachi S 900, ISI OS 130-F) characterized by an "in lens" position of the specimen where probe diameters are reduced and signal collection improved. Additionally, low voltage operation is extended to 1 kV. Compared to the first generation of FSEM (JE0L JSM 30, Hitachi S 800), which utilized a specimen position below the final lens, specimen size had to be reduced but useful magnification could be impressively increased in both low (1-4 kV) and high (5-40 kV) voltage operation, i.e. from 50,000 to 200,000 and 250,000 to 1,000,000 x respectively.At high accelerating voltage and magnification, contrasts on biological specimens are well characterized1 and are produced by the entering probe electrons in the outmost surface layer within -vl nm depth. Backscattered electrons produce only a background signal. Under these conditions (FIG. 1) image quality is similar to conventional TEM (FIG. 2) and only limited at magnifications >1,000,000 x by probe size (0.5 nm) or non-localization effects (%0.5 nm).

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Analysis of 6T SRAM Cell in Different Technologies

Circulation in Computer Science ◽

10.22632/ccs-2017-mcsp026 ◽

2017 ◽

Vol MCSP2017 (01) ◽

pp. 7-10 ◽

Cited By ~ 2

Author(s):

Subhashree Rath ◽

Siba Kumar Panda

Keyword(s):

Low Power ◽

Data Storage ◽

Low Voltage ◽

Random Access ◽

Storage Device ◽

Cmos Process ◽

Process Technology ◽

Digital Devices ◽

Noise Margin ◽

Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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Transient self back-biased buffer for low-voltage high-performance applications in standard CMOS technologies

Electronics Letters ◽

10.1049/el:19990116 ◽

1999 ◽

Vol 35 (2) ◽

pp. 112 ◽

Cited By ~ 3

Author(s):

Y. Moisiadis ◽

I. Bouras ◽

C. Papadas ◽

J.-P. Schoellkopf

Keyword(s):

High Performance ◽

Low Voltage

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A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401445 ◽

2021 ◽

Author(s):

Francesco Centurelli ◽

Giuseppe Scotti ◽

Alessandro Trifiletti ◽

Gaetano Palumbo

Keyword(s):

High Performance ◽

Low Voltage ◽

Frequency Divider

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Reliability-Oriented Design of Inverter-Fed Low-Voltage Electrical Machines: Potential Solutions

Energies ◽

10.3390/en14144144 ◽

2021 ◽

Vol 14 (14) ◽

pp. 4144

Author(s):

Yatai Ji ◽

Paolo Giangrande ◽

Vincenzo Madonna ◽

Weiduo Zhao ◽

Michael Galea

Keyword(s):

Power Density ◽

High Speed ◽

High Performance ◽

Low Voltage ◽

Electrical Machines ◽

Design Stage ◽

Switching Frequency ◽

Special Focus ◽

Electrical Machine ◽

Engineering Approach

Transportation electrification has kept pushing low-voltage inverter-fed electrical machines to reach a higher power density while guaranteeing appropriate reliability levels. Methods commonly adopted to boost power density (i.e., higher current density, faster switching frequency for high speed, and higher DC link voltage) will unavoidably increase the stress to the insulation system which leads to a decrease in reliability. Thus, a trade-off is required between power density and reliability during the machine design. Currently, it is a challenging task to evaluate reliability during the design stage and the over-engineering approach is applied. To solve this problem, physics of failure (POF) is introduced and its feasibility for electrical machine (EM) design is discussed through reviewing past work on insulation investigation. Then the special focus is given to partial discharge (PD) whose occurrence means the end-of-life of low-voltage EMs. The PD-free design methodology based on understanding the physics of PD is presented to substitute the over-engineering approach. Finally, a comprehensive reliability-oriented design (ROD) approach adopting POF and PD-free design strategy is given as a potential solution for reliable and high-performance inverter-fed low-voltage EM design.

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