scholarly journals Особенности роста слоев в напряженных сверхрешетках InAs/GaSb

2022 ◽  
Vol 48 (3) ◽  
pp. 10
Author(s):  
Р.В. Левин ◽  
В.Н. Неведомский ◽  
Л.А. Сокура
Keyword(s):  
Growth Temperature ◽  
Interface Layer ◽  
Layer Growth ◽  
Factors Affecting ◽  
Interface Layers ◽  
Transition Interface

The paper presents the results of a study of factors affecting the thickness of transition (interface) layers in stressed InAs/GaSb superlattices during growth by MOCVD method. It is shown that the thicknesses of the interface layers between InAs and GaSb are practically independent of the growth temperature. The thickness of the interface layers is influenced by the direction of switching the layer growth. The smallest thickness of 1.2-1.4 nm of the interface layer InAs/GaSb was obtained for the direction of growth switching from GaSb to InAs.

Characterization of Mg-Al Sheet Clad Materials Fabricated by Hot Rolling

2007 ◽  
Vol 26-28 ◽  
pp. 409-412 ◽  
Author(s):  
Jae Seol Lee ◽  
Hyeon Taek Son ◽  
Ki Yong Lee ◽  
Soon Sub Park ◽  
Dae Guen Kim ◽  
...  
Keyword(s):  
Tensile Strength ◽  
Vickers Hardness ◽  
Hot Rolling ◽  
High Strength ◽  
Interface Layer ◽  
Rolling Temperature ◽  
Al Alloy ◽  
Clad Sheet ◽  
The Difference ◽  
Interface Layers

AZ31 Mg / 5083 Al clad sheet was fabricated by the hot rolling method and its mechanical properties were investigated in this study. The tensile strength and yield strength of Mg- Al clad samples were slightly higher than that of AZ31 Mg sample, resulting in high strength 5083 Al alloy. Also, in the case of the AZ31 Mg sample, tensile strength indicated different values to the rolling directions. The thickness of interface layers between magnesium and aluminum materials increased with increasing rolling temperature. The thickness of interface layer was about 1.2 μm and 1.6 μm, respectively. The difference of thickness on the interface layer with variation of rolling temperature was attributed to promote the diffusion between magnesium and aluminum materials. The Vickers hardness of Mg-Al interface layer was around 125 Hv. The interface layer composed of hard inter-metallic phases which may act a increment of Vickers hardness depending upon its thickness.

Influence of InGaN layer growth temperature on luminescence properties of InGaN/GaN multiple quantum wells

2018 ◽  
Vol 5 (2) ◽  
pp. 025906 ◽  
Author(s):  
Xiaowei Wang ◽  
Jing Yang ◽  
Degang Zhao ◽  
Desheng Jiang ◽  
Zongshun Liu ◽  
...  
Keyword(s):  
Quantum Wells ◽  
Growth Temperature ◽  
Layer Growth ◽  
Multiple Quantum Wells ◽  
Luminescence Properties ◽  
Multiple Quantum ◽  
Ingan Layer

Impact of Buffered Layer Growth Conditions on Grown-In Vacancy Concentrations in Molecular Beam Epitaxy Silicon Germanium

2004 ◽  
Vol 809 ◽  
Author(s):  
Kareem M. Shoukri ◽  
Yaser M. Haddara ◽  
Andrew P. Knights ◽  
Paul G. Coleman ◽  
Mohammad M. Rahman ◽  
...  
Keyword(s):  
Molecular Beam Epitaxy ◽  
Buffer Layer ◽  
Point Defects ◽  
Growth Temperature ◽  
Silicon Germanium ◽  
Molecular Beam ◽  
Growth Conditions ◽  
Layer Growth ◽  
Vacancy Clusters ◽  
Temperature And Growth

ABSTRACTSilicon-Germanium (SiGe) has become increasingly attractive to semiconductor manufacturers over the last decade for use in high performance devices. In order to produce thin layers of device grade SiGe with low concentrations of point defects and well-controlled doping profiles, advanced growth and deposition techniques such as molecular beam epitaxy (MBE) are used. One of the key issues in modeling dopant diffusion during subsequent processing is the concentration of grown-in point defects. The incorporation of vacancy clusters and vacancy point defects in 200nm SiGe/Si layers grown by molecular beam epitaxy over different buffer layers has been observed using beam-based positron annihilation spectroscopy. Variables included the type of buffer layer, the growth temperature and growth rate for the buffer, and the growth temperature and growth rate for the top layer. Different growth conditions resulted in different relaxation amounts in the top layer, but in all samples the dislocation density was below 106 cm−2. Preliminary results indicate a correlation between the size, type and concentration of vacancy defects and the buffer layer growth temperature. At high buffer layer growth temperature of 500°C the vacancy point defect concentration is below the PAS detectable limit of approximately 1015 cm−3. As the buffer layer growth is decreased to a minimum value of 300°C, large vacancy clusters are observed in the buffered layer and vacancy point defects are observed in the SiGe film. These results are relevant to the role played by point defects grown-in at temperatures below ∼350°C in modeling dopant diffusion during processing.

Influences of Plasma Processed Interface Layers on Germanium MOS Devices with ALD Grown HfO2

2007 ◽  
Vol 996 ◽  
Author(s):  
Takuya Sugawara ◽  
Raghavasimhan Sreenivasan ◽  
Yasuhiro Oshima ◽  
Paul C. McIntyre
Keyword(s):  
Electrical Properties ◽  
Interface Layer ◽  
Hafnium Dioxide ◽  
Passivation Layer ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Layers ◽  
Silicon Based

AbstractGermanium and hafnium-dioxide (HfO2) stack structures' physical and electrical properties were studied based on the comparison of germanium and silicon based metal-oxide-semiconductor (MOS) capacitors' electrical properties. In germanium MOS capacitor with oxide/oxynitride interface layer, larger negative flat-band-voltage (Vfb) shift compared with silicon based MOS capacitors was observed. Secondary ion mass spectrum (SIMS) characteristics of HfO2-germanium stack structure with germanium oxynitride (GeON) interfacial layer showed germanium out diffusion into HfO2. These results indicate that the germanium out diffusion into HfO2 would be the origin of the germanium originated negative Vfb shift. Using Ta3N5 layer as a germanium passivation layer, reduced Vfb shift and negligible hysteresis were observed. These results suggest that the selection of passivation layer strongly influences the electrical properties of germanium based MOS devices.

The effect of spacer-layer growth temperature on mobility in a two-dimensional electron gas in PHEMT structures

2006 ◽  
Vol 40 (12) ◽  
pp. 1445-1449 ◽  
Author(s):  
G. B. Galiev ◽  
I. S. Vasil’evskiĭ ◽  
E. A. Klimov ◽  
V. G. Mokerov ◽  
A. A. Cherechukin
Keyword(s):  
Growth Temperature ◽  
Electron Gas ◽  
Layer Growth ◽  
Two Dimensional ◽  
Dimensional Electron ◽  
Two Dimensional Electron Gas ◽  
Spacer Layer ◽  
Dimensional Electron Gas

Dependence of GaN Defect Structure on the Growth Temperature of the AlN Buffer Layer

2008 ◽  
Vol 1068 ◽  
Author(s):  
Yuen-Yee Wong ◽  
Edward Yi Chang ◽  
Tsung-Hsi Yang ◽  
Jet-Rung Chang ◽  
Yi-Cheng Chen ◽  
...  
Keyword(s):  
Buffer Layer ◽  
Growth Temperature ◽  
Defect Structure ◽  
Defect Density ◽  
Layer Growth ◽  
Threading Dislocation ◽  
Higher Temperature ◽  
Lower Temperature ◽  
Aln Buffer ◽  
Gan Film

ABSTRACTThe defect structure of the GaN film grown on sapphire by plasma-assisted molecular beam epitaxy (PAMBE) technique was found to be dependent on the AlN buffer layer growth temperature. This buffer growth temperature controlled the defect density in GaN film but had shown contrary effects on the density of screw threading dislocation (TD) and edge TD. The density of screw TD was high on lower temperature buffer but low on the higher temperature buffer. Meanwhile the density of edge TD had shown the opposite. Further examinations have suggested that the defect structure was closely related to the stress in the GaN film, which can be controlled by the growth temperature of the AlN buffer. Using the 525°C AlN buffer, optimum quality GaN film with relatively low screw and edge TDs were achieved.

The effect of Ag electrode processing on (Nb, Ba) doped TiO2 ceramics

1990 ◽  
Vol 5 (7) ◽  
pp. 1530-1537 ◽  
Author(s):  
Chi-Jen Chen ◽  
Jenn-Ming Wu
Keyword(s):  
Dielectric Properties ◽  
Processing Condition ◽  
Temperature Stability ◽  
Relative Dielectric Constant ◽  
Dissipation Factor ◽  
Interface Layer ◽  
X Ray Diffraction ◽  
Ag Electrode ◽  
Ag Paste ◽  
Interface Layers

Since the characteristics of the electrode made from Ag paste greatly affect the dielectric properties of (Nb, Ba) doped TiO2 ceramics, the processing condition, i.e., baking temperature, was investigated. Low melting glass binder contained in Ag paste reacted with TiO2 ceramics to form an interface layer between Ag electrode and TiO2 ceramics during baking. The interface layer was identified as Bi2Ti2O7 by x-ray diffraction (XRD), and the thickness of the Bi2Ti2O7 layer was estimated from line profiles of EPMA and dielectric properties. The interface layers were found to increase with baking temperature. Increased baking temperature lowered the relative dielectric constant and dielectric dissipation factor of TiO2 ceramics, while it raised the resistivity. Controlling the baking condition of the Ag paste electrode on TiO2 ceramics resulted in reasonably good dielectric properties and excellent temperature stability.

Rutherford Backscattering Spectrometry Analysis of Growth Rate and Activation Energy for Self-formed Ti-rich Interface Layers in Cu(Ti)/Low-k Samples

2009 ◽  
Vol 1156 ◽  
Author(s):  
Kazuyuki Kohama ◽  
Kazuhiro Ito ◽  
Kenichi Mori ◽  
Kazuyoshi Maekawa ◽  
Yasuharu Shirai ◽  
...  
Keyword(s):  
Activation Energy ◽  
Dielectric Layer ◽  
Rutherford Backscattering Spectrometry ◽  
High Vacuum ◽  
Formation Enthalpy ◽  
Interface Layer ◽  
Rutherford Backscattering ◽  
Ultra High Vacuum ◽  
Dielectric Layers ◽  
Interface Layers

AbstractA new fabrication technique to prepare ultra-thin barrier layers for nano-scale Cu wires was proposed in our previous studies. Ti-rich layers formed at the Cu(Ti)/dielectric-layer interfaces consisted of crystalline TiC or TiSi and amorphous Ti oxides. The primary control factor for Ti-rich interface layer composition was the C concentration in the dielectric layers rather than the formation enthalpy of the Ti compounds. To investigate Ti-rich interface layer growth in Cu(Ti)/dielectric-layer samples annealed in ultra high vacuum, Rutherford Backscattering Spectrometry (RBS) was employed in the present study. Ti peaks were obtained only at the interface for all the samples. Molar amounts of Ti atoms segregated to the interface (n) were estimated from Ti peak areas. The n value was defined by n = Z·exp(-E/RT) · tm, where Z is a preexponential factor and E the activation energy for the reaction. The Z, E, and m values were estimated from plots of log n vs log t and log n vs 1/T. The m values are similar in all the samples. The E values for Ti atoms reacting with the dielectric layers containing carbon (except SiO2) tended to decrease with decreasing C concentration (decreasing k), while reaction rate coefficients (Z·exp(-E/RT)) were insensitive to C concentration in the dielectric layers. These factors lead to conclusion that growth of the Ti-rich interface layers is controlled by chemical reactions of the Ti atoms with the dielectric layers represented by the Z and E values, rather than diffusion in the Ti-rich interface layers.

ISSUES, ACHIEVEMENTS AND CHALLENGES TOWARDS INTEGRATION OF HIGH-k DIELECTRICS

2002 ◽  
Vol 12 (02) ◽  
pp. 295-304 ◽  
Author(s):  
M. CAYMAX ◽  
S. DE GENDT ◽  
W. VANDERVORST ◽  
M. HEYNS ◽  
H. BENDER ◽  
...  
Keyword(s):  
Carrier Mobility ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Interface Layer ◽  
Layer Growth ◽  
Electrical Characteristics ◽  
High K ◽  
Alternative Materials ◽  
High K Materials ◽  
Electrical Reliability

Once the thickness of the gate dielectric layer in CMOS devices gets thinner than 1.2 nm, excessive gate leakage due to direct tunneling makes the use of alternative materials obligatory. Candidate high-k materials are metal oxides such as Al 2 O 3, ZrO 2 and HfO 2 as well as their mixtures. Very promising results have been reported world-wide. Here, however, we show that there are a number of issues related to materials and electrical characteristics as well as to processing which are not always recognized and that necessitate more work to find solutions. Among these are problems with density, interface layer growth and island formation which are clearly related to the deposition process. Also thermal instabilities as well as interactions between the high-k material and poly-Si need attention. Further possible show-stoppers are electrical reliability issues and strongly reduced carrier mobility.

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