scholarly journals A 167.18 ppm/°C temperature coefficient, area efficient voltage reference using only MOS transistors

2020 ◽  
Vol 17 (1) ◽  
pp. 31-40
Author(s):  
Guru Prasad ◽  
Kumara Shama

In this paper, design of a voltage reference circuit using only MOS transistors and without employing an operational amplifier is presented. A proportional to absolute temperature [PTAT] voltage and a PTAT current are designed then difference of the PTAT voltage and product of the PTAT current and resistor gives the temperature independent voltage. The advantages of both sub-threshold and strong inversion region operation of MOS transistors are exploited in the design. The voltage reference is implemented using standard CMOS 180 nm technology. The voltage reference provides a voltage of 224.3 mV consuming a quiescent current of 30 ?A at room temperature. Post layout simulation results show that the proposed voltage reference has a temperature coefficient of 167.18 ppm/?C and varies only 3mV when there is a ?10% variation in supply voltage. The circuit occupies an area of only 93.6?32.6?m on the chip, making it suitable for area constraint applications.

2014 ◽  
Vol 519-520 ◽  
pp. 1067-1070
Author(s):  
Jian Ying Shi ◽  
Hui Ya Li ◽  
Yan Bin Xu

A no op amp structure full CMOS reference voltage circuit is designed. The two currents which are proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) are added together to get the reference output voltage which is obtained through a resistance. The characteristics of the new circuit are simulated using 0.5 μm BSIM3V3 spice models in HSPICE. The simulation results show that the output voltage of the circuit is 997mV, the power consumption is 1.12mW, the temperature coefficient is 15.2 ppm/°C in the range from-30°C to 100°C at the supply voltage of 2V.


2018 ◽  
Vol 27 (07) ◽  
pp. 1850105 ◽  
Author(s):  
Yuhua Liang ◽  
Zhangming Zhu

A low-power, low-supply, low-complexity all-MOSFET voltage reference is implemented in 0.18[Formula: see text][Formula: see text]m CMOS process. With the proposed architecture, the number of the transistors can be reduced to the greatest extent. As a result, the supply voltage can not only be decreased to as low as 0.7[Formula: see text]V, but the power consumption can also be optimized significantly. Simulation results show that the power consumption is 47[Formula: see text]nW, at a supply of 0.7[Formula: see text]V. A temperature coefficient (TC) of 42[Formula: see text]ppm/[Formula: see text]C is achieved when the temperature ranges from [Formula: see text]20[Formula: see text]C to 80[Formula: see text]C. At room temperature, the voltage reference features a line regulation (LR) of 2.66%/V.


2018 ◽  
Vol 27 (08) ◽  
pp. 1850128 ◽  
Author(s):  
R. Nagulapalli ◽  
K. Hayatleh ◽  
Steve Barker ◽  
Sumathi Raparthy ◽  
Nabil Yassine ◽  
...  

This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65[Formula: see text]nm CMOS has been developed and occupies 0.0039[Formula: see text]mm2, and at room temperature, it generates a 204[Formula: see text]mV reference voltage with 1.3[Formula: see text]mV drift over a wide temperature range (from [Formula: see text]40[Formula: see text]C to 125[Formula: see text]C). This has been designed to operate with a power supply voltage down to 0.6[Formula: see text]V and consumes 1.8[Formula: see text]uA current from the supply. The simulated temperature coefficient is 40[Formula: see text]ppm/[Formula: see text]C.


2012 ◽  
Vol 588-589 ◽  
pp. 839-842 ◽  
Author(s):  
Zhi Cheng Hu ◽  
Zhi Hua Ning ◽  
Le Nian He

A low temperature coefficient, high voltage detection circuit used in Power over Ethernet is proposed. This circuit realizes the detection comparison without utilizing an extra voltage reference circuit and comparator while the temperature coefficient of the threshold voltage is as low as that of a regular bandgap reference. The proposed detection circuit is implemented in CSMC 0.5μm 60V BCD process, Cadence Spectre simulation results show that the temperature coefficient of the threshold voltage is 66.5 ppm/°C over the temperature range of -40°C to 125°C, and the maximum variation of the threshold voltage is 2.7% under all corners.


2014 ◽  
Vol 23 (08) ◽  
pp. 1450107 ◽  
Author(s):  
JUN-DA CHEN ◽  
CHENG-KAI YE

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 μm standard CMOS process. We design the first-order temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596 V and achieves the reported temperature coefficient (TC) of 3.96 ppm/°C within the temperature range from -60°C to 130°C when the supply voltage is 1.8 V. When simulated in a smaller temperature range from -40°C to 80°C, the circuit achieves the lowest reported TC of 2.09 ppm/°C. The reference current is 16.586 μA. This circuit provides good performances in a wide range of temperature with very small TC.


Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1271
Author(s):  
Brito ◽  
Colombo ◽  
Moreno ◽  
El-Sankary

This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, a new circuit topology of a resistorless voltage reference circuit using a Schottky diode is also presented. The circuit was fabricated in a 130 nm BiCMOS process and occupied a silicon area of 67.98 µm × 161.7 µm. The averaged value of the output voltage is 720.4 mV, and its averaged line regulation performance is 2.3 mV/V, calculated through 26 characterized chip samples. The averaged temperature coefficient (TC) obtained through five chip samples is 56 ppm/°C in a temperature range from −40 to 85°C. A trimming circuit is also included in the circuit topology to mitigate the impact of the fabrication process effects on its TC. The circuit operates with a supply voltage range from 1.1 to 2.5 V.


2014 ◽  
Vol 989-994 ◽  
pp. 1165-1168
Author(s):  
Qian Neng Zhou ◽  
Yun Song Li ◽  
Jin Zhao Lin ◽  
Hong Juan Li ◽  
Chen Li ◽  
...  

A high-order bandgap voltage reference (BGR) is designed by adopting a current which is proportional to absolute temperature T1.5. The high-order BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the designed high-order BGR achieves temperature coefficient of 2.54ppm/°C when temperature ranging from-55°C to 125°C. The high-order BGR at 10Hz, 100Hz, 1kHz, 10kHz and 100kHz achieves, respectively, the power supply rejection ratio of-64.01dB, -64.01dB, -64dB, -63.5dB and-53.2dB. When power supply voltage changes from 1.7V to 2.5V, the output voltage deviation of BGR is only 617.6μV.


2012 ◽  
Vol 503 ◽  
pp. 12-17
Author(s):  
Qiang Li ◽  
Xiao Yun Tan ◽  
Guan Shi Wang

The reference is an important part of the micro-gyroscope system. The precision and stability of the reference directly affect the precision of the micro-gyroscope. Unlike the traditional bandgap reference circuit, a circuit using a temperature-dependent resistor ratio generated by a highly-resistive poly resistor and a diffusion resistor in CMOS technology is proposed in this paper. The complexity of the circuit is greatly reduced. Implemented with the standard 0.5μm CMOS technology and 9V power supply voltage, in the range of -40~120°C, the temperature coefficient of the proposed bandgap voltage reference can achieve to about 1.6 ppm/°C. The PSRR of the circuit is -107dB.


Author(s):  
Mohammadreza Rasekhi ◽  
Emad Ebrahimi ◽  
Hamed Aminzadeh

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.


Sign in / Sign up

Export Citation Format

Share Document