A New No Op Amp Full CMOS Voltage Reference Circuit

2014 ◽  
Vol 519-520 ◽  
pp. 1067-1070
Author(s):  
Jian Ying Shi ◽  
Hui Ya Li ◽  
Yan Bin Xu
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Output Voltage ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Op Amp ◽  
Reference Circuit ◽  
Simulation Results ◽  
Cmos Voltage Reference

A no op amp structure full CMOS reference voltage circuit is designed. The two currents which are proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) are added together to get the reference output voltage which is obtained through a resistance. The characteristics of the new circuit are simulated using 0.5 μm BSIM3V3 spice models in HSPICE. The simulation results show that the output voltage of the circuit is 997mV, the power consumption is 1.12mW, the temperature coefficient is 15.2 ppm/°C in the range from-30°C to 100°C at the supply voltage of 2V.

scholarly journals A 167.18 ppm/°C temperature coefficient, area efficient voltage reference using only MOS transistors

2020 ◽  
Vol 17 (1) ◽  
pp. 31-40
Author(s):  
Guru Prasad ◽  
Kumara Shama
Keyword(s):  
Temperature Coefficient ◽  
Room Temperature ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Inversion Region ◽  
Strong Inversion ◽  
Reference Circuit ◽  
Simulation Results

In this paper, design of a voltage reference circuit using only MOS transistors and without employing an operational amplifier is presented. A proportional to absolute temperature [PTAT] voltage and a PTAT current are designed then difference of the PTAT voltage and product of the PTAT current and resistor gives the temperature independent voltage. The advantages of both sub-threshold and strong inversion region operation of MOS transistors are exploited in the design. The voltage reference is implemented using standard CMOS 180 nm technology. The voltage reference provides a voltage of 224.3 mV consuming a quiescent current of 30 ?A at room temperature. Post layout simulation results show that the proposed voltage reference has a temperature coefficient of 167.18 ppm/?C and varies only 3mV when there is a ?10% variation in supply voltage. The circuit occupies an area of only 93.6?32.6?m on the chip, making it suitable for area constraint applications.

DESIGN OF A CMOS BANDGAP REFERENCE CIRCUIT WITH A WIDE TEMPERATURE RANGE, HIGH PRECISION AND LOW TEMPERATURE COEFFICIENT

2014 ◽  
Vol 23 (08) ◽  
pp. 1450107 ◽  
Author(s):  
JUN-DA CHEN ◽  
CHENG-KAI YE
Keyword(s):  
Temperature Coefficient ◽  
High Precision ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Range ◽  
Wide Range ◽  
Bandgap Voltage Reference ◽  
Reference Circuit ◽  
Cmos Voltage Reference

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 μm standard CMOS process. We design the first-order temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596 V and achieves the reported temperature coefficient (TC) of 3.96 ppm/°C within the temperature range from -60°C to 130°C when the supply voltage is 1.8 V. When simulated in a smaller temperature range from -40°C to 80°C, the circuit achieves the lowest reported TC of 2.09 ppm/°C. The reference current is 16.586 μA. This circuit provides good performances in a wide range of temperature with very small TC.

A 42ppm/∘C 0.7V 47nW Low-Complexity All-MOSFET Sub-Threshold Voltage Reference

2018 ◽  
Vol 27 (07) ◽  
pp. 1850105 ◽  
Author(s):  
Yuhua Liang ◽  
Zhangming Zhu
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Supply Voltage ◽  
Low Complexity ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Ranges ◽  
Simulation Results

A low-power, low-supply, low-complexity all-MOSFET voltage reference is implemented in 0.18[Formula: see text][Formula: see text]m CMOS process. With the proposed architecture, the number of the transistors can be reduced to the greatest extent. As a result, the supply voltage can not only be decreased to as low as 0.7[Formula: see text]V, but the power consumption can also be optimized significantly. Simulation results show that the power consumption is 47[Formula: see text]nW, at a supply of 0.7[Formula: see text]V. A temperature coefficient (TC) of 42[Formula: see text]ppm/[Formula: see text]C is achieved when the temperature ranges from [Formula: see text]20[Formula: see text]C to 80[Formula: see text]C. At room temperature, the voltage reference features a line regulation (LR) of 2.66%/V.

scholarly journals CMOS Voltage Reference using a Self-Cascode Composite Transistor and a Schottky Diode

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1271
Author(s):  
Brito ◽  
Colombo ◽  
Moreno ◽  
El-Sankary
Keyword(s):  
Schottky Diode ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Silicon Area ◽  
Circuit Topology ◽  
Voltage Range ◽  
Self Cascode ◽  
Cmos Voltage Reference ◽  
The Impact

This work presents an investigation of the temperature behavior of self-cascode composite transistors (SCCTs). Results supported by silicon measurements show that SCCTs can be used to generate a proportional to absolute temperature voltage or even a temperature-compensated voltage. Based on the achieved results, a new circuit topology of a resistorless voltage reference circuit using a Schottky diode is also presented. The circuit was fabricated in a 130 nm BiCMOS process and occupied a silicon area of 67.98 µm × 161.7 µm. The averaged value of the output voltage is 720.4 mV, and its averaged line regulation performance is 2.3 mV/V, calculated through 26 characterized chip samples. The averaged temperature coefficient (TC) obtained through five chip samples is 56 ppm/°C in a temperature range from −40 to 85°C. A trimming circuit is also included in the circuit topology to mitigate the impact of the fabrication process effects on its TC. The circuit operates with a supply voltage range from 1.1 to 2.5 V.

3.48-nW 58.4ppm/∘C Sub-threshold CVR with Four Transistors and Two Resistors

2021 ◽  
Author(s):  
Mohammadreza Rasekhi ◽  
Emad Ebrahimi ◽  
Hamed Aminzadeh
Keyword(s):  
Process Variations ◽  
Mean Value ◽  
Absolute Temperature ◽  
Reference Voltage ◽  
Cmos Process ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Low Power Cmos ◽  
Simulation Results ◽  
Cmos Voltage Reference

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

A low-voltage, low-power voltage reference based on subthreshold MOSFETs

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740069 ◽  
Author(s):  
Liangwei Dong ◽  
Yueli Hu
Keyword(s):  
Low Power ◽  
Temperature Coefficient ◽  
High Performance ◽  
Low Voltage ◽  
Supply Voltage ◽  
Channel Length ◽  
Voltage Reference ◽  
Single Chip ◽  
Low Power Cmos ◽  
Cmos Voltage Reference

A novel low-voltage low-power CMOS voltage reference independent of temperature is presented in this design. After considering the combined effect of (1) a perfect suppression of the temperature dependence of mobility; (2) the compensation of the channel length modulation effect on the temperature coefficient, a temperature coefficient of 10 ppm/[Formula: see text]C is achieved. Moreover, by adopting the subthreshold MOSFETs, there are no resistors used in the proposed structure. Therefore, the maximum supply current measured at the maximum supply voltage is 70 nA and at 80[Formula: see text]C. The circuit can be used as a voltage reference for high performance and low power dissipation on a single chip.

A Low Temperature Coefficient, High Voltage Detection Circuit Used in Power over Ethernet

2012 ◽  
Vol 588-589 ◽  
pp. 839-842 ◽  
Author(s):  
Zhi Cheng Hu ◽  
Zhi Hua Ning ◽  
Le Nian He
Keyword(s):  
Low Temperature ◽  
Temperature Coefficient ◽  
High Voltage ◽  
Threshold Voltage ◽  
Bandgap Reference ◽  
Voltage Reference ◽  
Temperature Range ◽  
Detection Circuit ◽  
Reference Circuit ◽  
Simulation Results

A low temperature coefficient, high voltage detection circuit used in Power over Ethernet is proposed. This circuit realizes the detection comparison without utilizing an extra voltage reference circuit and comparator while the temperature coefficient of the threshold voltage is as low as that of a regular bandgap reference. The proposed detection circuit is implemented in CSMC 0.5μm 60V BCD process, Cadence Spectre simulation results show that the temperature coefficient of the threshold voltage is 66.5 ppm/°C over the temperature range of -40°C to 125°C, and the maximum variation of the threshold voltage is 2.7% under all corners.

Design of a Sub-0.4 V Reference Circuit in 0.18μm CMOS Technology

2013 ◽  
Vol 816-817 ◽  
pp. 882-886 ◽  
Author(s):  
Sonal Singhal ◽  
Rohit Singh ◽  
Amit Kumar Singh
Keyword(s):  
Temperature Dependence ◽  
Output Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Threshold Current ◽  
Total Current ◽  
Voltage Reference ◽  
Threshold Voltages ◽  
Reference Generator ◽  
Reference Circuit

This paper proposes a low power voltage reference generator in 0.18μm CMOS technology.The circuit presented here includes MOSFETs in sub threshold mode and uses the temperature dependence of threshold voltages and sub-threshold current of MOSFET to form a temperature-insensitive reference. An input supply voltage of 1.8 Volt is used for the circuit generating a total current of 1.33μA. By varying the device temperature over the range of-20°C to 100°C corresponding variation over the output voltage was found to lie in the range 397.8 to 400.2 mV. Thus a 0.6% variation in voltage over the considered range of temperature is obtained.

scholarly journals A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout Voltage for Sensor Circuits

Sensors ◽  
2021 ◽  
Vol 21 (23) ◽  
pp. 7856
Author(s):  
Jianyu Zhang ◽  
Pak Kwong Chan
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Output Voltage ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Process Technology ◽  
Operation Condition ◽  
Worst Case ◽  
Operation Temperature

A new power supply rejection (PSR) based enhancer with small and stable dropout voltage is presented in this work. It is implemented using TSMC-40 nm process technology and powered by 1.2 V supply voltage. A number of circuit techniques are proposed in this work. These include the temperature compensation for Level-Shifted Flipped Voltage Follower (LSFVF) and the Complementary-To-Absolute Temperature (CTAT) current reference. The typical output voltage and dropout voltage of the enhancer is 1.1127 V and 87.3 mV, respectively. The Monte-Carlo simulation of this output voltage yields a mean T.C. of 29.4 ppm/°C from −20 °C and 80 °C. Besides, the dropout voltage has been verified with good immunity against Process, Temperature and Process (PVT) variation through the worst-case simulation. Consuming only 4.75 μA, the circuit can drive load up to 500 μA to yield additional PSR improvement of 36 dB and 20 dB of PSR at 1 Hz and 1 MHz, respectively for the sensor circuit of interest. This is demonstrated through the application of an enhancer on the instrumentation Differential Difference Amplifier (DDA) for sensing floating bridge sensor signal. The comparative Monte-Carlo simulation results on a respective DDA circuit have revealed that the process sensitivity of output voltage of this work has achieved 14 times reduction in transient metrics with respect to that of the conventional counterpart over the operation temperature range in typical operation condition. Due to simplicity without voltage reference and operational amplifier(s), low power and small consumption of supply voltage headroom, the proposed work is very useful for supply noise sensitive analog or sensor circuit applications.

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