scholarly journals The Influence of Back Gate Bias on the OCTO SOI MOSFET’s Response to X-ray Radiation

2015 ◽  
Vol 10 (1) ◽  
pp. 43-48
Author(s):  
Leonardo N. de S. Fino ◽  
Marcilei A. Guazzelli ◽  
Christian Renaux ◽  
Denis Flandre ◽  
Salvador P. Gimenez
Keyword(s):  
Comparative Analysis ◽  
Gate Bias ◽  
Electrical Behavior ◽  
Total Ionizing Dose ◽  
Back Gate ◽  
Soi Mosfet ◽  
X Ray ◽  
Buried Oxide ◽  
Threshold Voltages ◽  
The One

This work investigates the X-ray irradiation impact on the performance of an on-conventional transistor called OCTO SOI MOSFET that adopts an octagonal gate shape instead of a rectangular. The electrical behaviors of both devices were studied through an experimental comparative analysis of the total ionizing dose influence. In addition, the back-gate bias technique was applied in these devices to reestablish its threshold voltages and drain currents conditions that were degraded due the trapping of positive charges in the buried oxide. As the main finding of this work, after the irradiation procedure, we notice that the OCTO device is capable to reestablish its pre-rad electrical behavior with a smaller back gate bias than the one observed in the standard one counterpart. This is mainly because the parasitic transistors in the bird’s beak region are practically deactivated due the particular octagonal gate geometry.

Impact of Back-Gate Bias and Device Geometry on the Total Ionizing Dose Response of 1-Transistor Floating Body RAMs

2012 ◽  
Vol 59 (6) ◽  
pp. 2966-2973 ◽  
Author(s):  
N. N. Mahatme ◽  
E. X. Zhang ◽  
R. A. Reed ◽  
B. L. Bhuva ◽  
R. D. Schrimpf ◽  
...  
Keyword(s):  
Dose Response ◽  
Floating Body ◽  
Gate Bias ◽  
Total Ionizing Dose ◽  
Back Gate ◽  
Device Geometry

scholarly journals Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors

2020 ◽  
Vol 15 (1) ◽  
pp. 1-6
Author(s):  
Fernando José Costa ◽  
Renan Trevisoli Doria ◽  
Rodrigo Trevisoli Doria
Keyword(s):  
Experimental Data ◽  
Ground Plane ◽  
Capacitive Coupling ◽  
Thin Body ◽  
Substrate Effect ◽  
Gate Bias ◽  
Effect Evaluation ◽  
Back Gate ◽  
Buried Oxide

The main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to experimental data. Different ground plane (GP) arrangements have been considered in order to enhance the analysis. It has been shown that the substrate effect is strongly influenced by the reduction of the back gate bias and, that the capacitive coupling of the structure presents a different behavior with respect of each kind of GP configuration as the back gate bias is varied. Finally, it has been shown that the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the transistors.

scholarly journals Parasitic Conduction Response to X-ray Radiation in Unstrained and Strained Triple-Gate SOI MuGFETs

2014 ◽  
Vol 9 (2) ◽  
pp. 97-102
Author(s):  
Fernando F. Teixeira ◽  
Caio C. M. Bordallo ◽  
Marcilei A. Guazzelli ◽  
Paula Ghedini Der Agopian ◽  
João Antonio Martino ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Drain Current ◽  
X Rays ◽  
Back Gate ◽  
X Ray ◽  
Dose Rates ◽  
Buried Oxide ◽  
Opposite Trend

In this work, the X-ray irradiation impact on the back gate conduction and drain current for Triple-Gate SOI FinFETs is investigated for strained and unstrained devices. Both types (P and N) of transistors were analyzed. Since X-rays promote trapped positive charges in the buried oxide, the second interface threshold voltage shifts to lower gate voltage. The performance of n-channel devices presented a strong degradation when submitted to X-rays, while for p-channel devices the opposite trend was observed. Two different dose rates were analyzed.

Stable high-density FD/SOI SRAM with selective back-gate bias using dual buried oxide

2008 ◽  
Author(s):  
Keunwoo Kim ◽  
Jente B. Kuang ◽  
Fadi Gebara ◽  
Hung C. Ngo ◽  
Ching-Te Chuang ◽  
...  
Keyword(s):  
High Density ◽  
Gate Bias ◽  
Back Gate ◽  
Buried Oxide

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Sign in / Sign up

Export Citation Format

Share Document