Effectiveness of using supply voltage as back-gate bias in ground plane SOI MOSFET

2005 ◽  
Author(s):  
C.H. Kim ◽  
H. Ananthan ◽  
Jae-Joon Kim ◽  
K. Roy
Keyword(s):  
Supply Voltage ◽  
Ground Plane ◽  
Gate Bias ◽  
Back Gate ◽  
Soi Mosfet

scholarly journals Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors

2020 ◽  
Vol 15 (1) ◽  
pp. 1-6
Author(s):  
Fernando José Costa ◽  
Renan Trevisoli Doria ◽  
Rodrigo Trevisoli Doria
Keyword(s):  
Experimental Data ◽  
Ground Plane ◽  
Capacitive Coupling ◽  
Thin Body ◽  
Substrate Effect ◽  
Gate Bias ◽  
Effect Evaluation ◽  
Back Gate ◽  
Buried Oxide

The main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to experimental data. Different ground plane (GP) arrangements have been considered in order to enhance the analysis. It has been shown that the substrate effect is strongly influenced by the reduction of the back gate bias and, that the capacitive coupling of the structure presents a different behavior with respect of each kind of GP configuration as the back gate bias is varied. Finally, it has been shown that the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the transistors.

scholarly journals The Influence of Back Gate Bias on the OCTO SOI MOSFET’s Response to X-ray Radiation

2015 ◽  
Vol 10 (1) ◽  
pp. 43-48
Author(s):  
Leonardo N. de S. Fino ◽  
Marcilei A. Guazzelli ◽  
Christian Renaux ◽  
Denis Flandre ◽  
Salvador P. Gimenez
Keyword(s):  
Comparative Analysis ◽  
Gate Bias ◽  
Electrical Behavior ◽  
Total Ionizing Dose ◽  
Back Gate ◽  
Soi Mosfet ◽  
X Ray ◽  
Buried Oxide ◽  
Threshold Voltages ◽  
The One

This work investigates the X-ray irradiation impact on the performance of an on-conventional transistor called OCTO SOI MOSFET that adopts an octagonal gate shape instead of a rectangular. The electrical behaviors of both devices were studied through an experimental comparative analysis of the total ionizing dose influence. In addition, the back-gate bias technique was applied in these devices to reestablish its threshold voltages and drain currents conditions that were degraded due the trapping of positive charges in the buried oxide. As the main finding of this work, after the irradiation procedure, we notice that the OCTO device is capable to reestablish its pre-rad electrical behavior with a smaller back gate bias than the one observed in the standard one counterpart. This is mainly because the parasitic transistors in the bird’s beak region are practically deactivated due the particular octagonal gate geometry.

scholarly journals Ground Plane Influence on Analog Parameters of Different UTBB nMOSFET Technologies

2017 ◽  
Vol 12 (2) ◽  
pp. 82-88
Author(s):  
V. T. Itocazu ◽  
V. Sonnenberg ◽  
J. A. Martino ◽  
E. Simoen ◽  
Cor Clayes
Keyword(s):  
Gate Dielectric ◽  
Dielectric Material ◽  
Ground Plane ◽  
Silicon Film ◽  
Gate Bias ◽  
Back Gate ◽  
Analog Performance ◽  
Long Channel ◽  
Gate Dielectric Material ◽  
Analog Parameters

This paper presents an analysis of the silicon film thickness (6 nm and 14 nm), the gate dielectric material (SiO2 and High- κ material) and the Ground Plane influence on the analog parameters of Ultra Thin Body and Buried Oxide (UTBB) SOl nMOSFET devices, based on experimental and simulation results. Two channel lengths (70 nm and 1μm) have been considered and the analog performance has been analyzed as a function of the back gate bias. It is shown that at zero back gate bias , the presence of a Ground Plane improves the transconductance in the saturation region due to the strong coupling between front and back gates in devices with a long channel (1 μm), thin silicon film (6 nm) and SiO2 as gate dielectric material. However, for the intrinsic voltage gain, output conductance and Early Voltage, the devices without Ground Plane present better results due to the higher drain electrical field penetration. Short-channel transistors (70 nm) with Ground Plane show an improvement of the analog parameters also due to the high drain electrical field penetration. Similar behavior is noticed in devices with a thicker silicon film (14nm). UTBB nMOSFETs with High- κ material present less influence of a Ground Plane on the parameters analyzed. Varying the back gate bias in devices with long channel (1 μm) and SiO2 as gate dielectric material, the analog parameters present better results in devices without Ground Plane, except for the transconductance in long channel transistors with a thin silicon film, for the reason explained before (strong coupling between front and back gates). Devices with High-κ material as gate dielectric show a minor improvement of the analog performance with a Ground Plane.

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

A Very Low Power Quadrature VCO with Modified Current-Reuse and Back-Gate Coupling Topology

2017 ◽  
Vol 26 (11) ◽  
pp. 1750184 ◽  
Author(s):  
Qiuzhen Wan ◽  
Jun Dong ◽  
Hui Zhou ◽  
Fei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Current Reuse ◽  
Quadrature Vco ◽  
In Series

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.

scholarly journals A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 69 ◽  
Author(s):  
Taufiq Alif Kurniawan ◽  
Toshihiko Yoshimasu
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Back Gate ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

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