In-Situ Electrical Monitoring and Contactless Measurement Techniques for Enhanced FIB Modifications

1998 ◽  
Author(s):  
Romain Desplats ◽  
Jamel Benbrik ◽  
Philippe Perdu ◽  
Bruno Benteo ◽  
François Marc ◽  
...  
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Measurement Techniques ◽  
Contactless Measurement ◽  
Design Modification ◽  
Area Of Interest ◽  
Milling Operations ◽  
Voltage Contrast ◽  
Metal Layers

Abstract Recent planar technologies with 3 metal layers or more challenge current physical design modification capacities using Focused Ion Beam tools. Image visibility on the FIB is drastically reduced, making accurate positioning and milling operations in the area of interest more difficult, and the use of power planes increases the risk of short circuits while accessing inferior metal lines. Despite the complexity of FIB modifications, however, the demand for circuit modifications continues to increase. To respond to this demand for successful, time efficient, FIB modifications, step by step monitoring of operations is imperative. In this paper, we will present an innovative method which brings in-situ electrical monitoring and contactless measurement capabilities to FIB systems. Electrical connection of the circuit inside the vacuum FIB chamber is done using a commercial load module and logic waveform acquisition with the FIB is obtained without modifying FIB hardware using a voltage contrast approach. With this method, it is possible to verify the completion of FIB milling and depositing operations by temporarily suspending FIB action so that a test pattern can be run allowing electrical testing and measurements of the circuit without damaging it.

Investigations of Leakage Paths in Sub-0.35μm DRAM Products Using Advanced Focused Ion Beam Techniques

1998 ◽  
Author(s):  
H. Lorenz ◽  
C. Engel
Keyword(s):  
Focused Ion Beam ◽  
Cell Function ◽  
Dielectric Breakdown ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Floating Gate ◽  
Leakage Path ◽  
Contrast Technique ◽  
Voltage Contrast

Abstract Due to the continuously decreasing cell size of DRAMs and concomitantly diminishing thickness of some insulating layers new failure mechanisms appear which until now had no significance for the cell function. For example high resistance leakage paths between closely spaced conductors can lead to retention problems. These are hard to detect by electrical characterization in a memory tester because the involved currents are in the range of pA. To analyze these failures we exploit the very sensitive passive voltage contrast of the Focused Ion Beam Microscope (FIB). The voltage contrast can further be enhanced by in-situ FIB preparations to obtain detailed information about the failure mechanism. The first part of this paper describes a method to detect a leakage path between a borderless contact on n-diffusion and an adjacent floating gate by passive voltage contrast achieved after FIB circuit modification. In the second part we will demonstrate the localization of a DRAM trench dielectric breakdown. In this case the FIB passive voltage contrast technique is not limited to the localization of the failing trench. We can also obtain the depth of the leakage path by selective insitu etching with XeF2 stopped immediately after a voltage contrast change.

Electron beam testing of multilevel metal integrated circuits

1991 ◽  
Vol 49 ◽  
pp. 830-831
Author(s):  
P. E. Russell ◽  
Z. J. Radzimski ◽  
D. A. Ricks ◽  
J. P. Vitarelli
Keyword(s):  
Electron Beam ◽  
Integrated Circuits ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Measurement Techniques ◽  
Ion Beam Etching ◽  
Voltage Contrast ◽  
Modelling Effort ◽  
Established Technique

Fundamentally, voltage contrast is a well established technique for determination of voltages on metal surface which can be directly probed with an electron beam. However, actual integrated circuits (IC) consist of two or more conducting layers (metal and doped polysilicon) separated by dielectrics and covered by a dielectric passivation layer. Our work has addressed: i) the removal of dielectric layers (depassivation) by reactive ion etching (RIE) or selectively by focused ion beam etching to allow access to exposed metal lines; ii) modelling effort to understand how the materials and geometric parameters of multilevel IC's affect voltage contrast measurements, and iii) improvements in retarding field spectrometer based measurement techniques.

scholarly journals Application of FIB/SEM and TEM to Bit Failure Analyses in SRAM Arrays

2003 ◽  
Vol 782 ◽  
Author(s):  
Wentao Qin ◽  
Alex Volinsky ◽  
Larry Rice ◽  
Lorraine Johnston ◽  
David Theodore
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Embedded Memory ◽  
Area Of Interest ◽  
Microelectronic Devices ◽  
Dual Beam ◽  
Sem Imaging ◽  
Lift Off ◽  
Failure Site

ABSTRACTMany microelectronic chips contain embedded memory arrays. A single SRAM bit-cell contains several transistors. Failure of any of the transistors makes the entire bit-cell inoperable. Dual-beam Focused Ion Beam (FIB) combines the slicing capability of FIB with in-situ SEM imaging. The combination offers unparalleled precision in looking for root causes of failures in microelectronic devices. Once a failure site is located, an FIB lift-off method can be used to prepare a TEM sample containing the area of interest. Further structural, elemental information can then be acquired from the failure site. We report here analyses of single and multiple bit failures in SRAM arrays carried out using FIB/SEM, and in two cases TEM imaging and EDS/PEELS. Root causes of bit failures including remnant seed-layer metal between stacked vias have been identified.

scholarly journals FA Approach on MIM (Metal-Insulator-Metal) Capacitor Failures

2021 ◽  
Author(s):  
Kuang Shien Lee ◽  
Lai Khei Kuan
Keyword(s):  
Computer Aided Design ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Metal Insulator ◽  
Isolation Techniques ◽  
Metal Insulator Metal ◽  
The Difference ◽  
Voltage Contrast ◽  
Metal Layers

Abstract MIM (Metal-Insulator-Metal) capacitor is a capacitor fabricated between metal layers and usually in an array form. Since it is usually buried within stack of back-end metal layers, neither front side nor backside FA fault isolation techniques can easily pinpoint the defect location of a failing MIM capacitor. A preliminary fault isolation (FI) often needs to be performed by biasing the desired failing state setup to highlight the difference(s) of FI site(s) between failing unit & reference. Then, a detailed study of the CAD (Computer Aided Design) schematic and die layout focusing on the difference(s) of FI site(s) will lead to a more in-depth analyses such as Focused Ion-Beam (FIB) circuit edit, micro-probing/nano-probing, Voltage Contrast (VC) and other available FA techniques to further identify the defective MIM capacitor. Once the defective MIM capacitor was identified, FIB cross-section or delayering can be performed to inspect the physical defect on the MIM capacitor. This paper presents the FA approach and challenges in successfully finding MIM capacitor failures.

Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration

2000 ◽  
Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet
Keyword(s):  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Devices ◽  
Front Side ◽  
Automatic Determination ◽  
Metal Line ◽  
New Approach ◽  
Metal Layers

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.

Analysis of Voltage Contrast in Secondary Electron Images Using a High-Energy Electron Spectrometer

2019 ◽  
Author(s):  
Natsuko Asano ◽  
Shunsuke Asahina ◽  
Natasha Erdman
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Sample Surface ◽  
High Energy ◽  
Secondary Electrons ◽  
Analysis Technique ◽  
Quantitative Understanding ◽  
Voltage Contrast ◽  
Acceleration Voltage ◽  
Failure Localization

Abstract Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

To Eliminate Curtain Effect of FIB TEM Samples by a Combination of Sample Dicing and Backside Milling

2014 ◽  
Author(s):  
Jian-Shing Luo ◽  
Hsiu Ting Lee
Keyword(s):  
Sample Preparation ◽  
Focused Ion Beam ◽  
Preparation Method ◽  
Low Cost ◽  
Ion Beam ◽  
Sample Preparation Method ◽  
Site Specific ◽  
Dual Beam ◽  
Transmission Electron

Abstract Several methods are used to invert samples 180 deg in a dual beam focused ion beam (FIB) system for backside milling by a specific in-situ lift out system or stages. However, most of those methods occupied too much time on FIB systems or requires a specific in-situ lift out system. This paper provides a novel transmission electron microscopy (TEM) sample preparation method to eliminate the curtain effect completely by a combination of backside milling and sample dicing with low cost and less FIB time. The procedures of the TEM pre-thinned sample preparation method using a combination of sample dicing and backside milling are described step by step. From the analysis results, the method has applied successfully to eliminate the curtain effect of dual beam FIB TEM samples for both random and site specific addresses.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

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