Application of Standard Metallurgical Analytical Techniques to Improve High Temperature Operational Life Performance of Bump Interconnect Technology of Flip Chip Packaging

1998 ◽  
Author(s):  
Kendall Scott Wills ◽  
John Abbott ◽  
Chris Carty ◽  
Rohini Raghunathan ◽  
Philip Simon ◽  
...  
Keyword(s):  
High Temperature ◽  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Analytical Techniques ◽  
Analysis Techniques ◽  
Operational Life ◽  
Flip Chip Packaging ◽  
Interconnect Technology

Abstract Flip Chip packaging requires an understanding of the solder bump metallurgy and its aging characteristics. In this paper we demonstrate how standard failure analysis techniques can help determine aging characteristics and, how an understanding of bump age can be successfully employed to enhance bump reliability.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

Flip-Chip Ball Grid Array Lead-Free Solder Joint Under Reliability Test

2005 ◽  
Vol 127 (4) ◽  
pp. 446-451 ◽  
Author(s):  
Ming-Hwa R. Jen ◽  
Lee-Cheng Liu ◽  
Jenq-Dah Wu
Keyword(s):  
Mechanical Properties ◽  
High Temperature ◽  
Service Time ◽  
Flip Chip ◽  
Failure Modes ◽  
Mechanical Responses ◽  
Operational Life ◽  
Different Temperatures ◽  
Free Solder

The work is aimed to investigate the mechanical responses of bare dies of the combination of pure tin∕Al–NiV–Cu Under bump metallization (UBM) and packages of pure tin∕Al–NiV–Cu UBM/substrate of standard thickness of aurum. The mechanical properties under multiple reflow and long term high temperature storage test (HTST) tests at different temperatures and the operational life were obtained. A scanning electron microscope was used to observe the growth of IMC and the failure modes in order to realize their reaction and connection. From the empirical results of bare dies, the delamination between IMC and die was observed due to the tests at 260 °C multiple reflow. However, their mechanical properties were not affected. Nevertheless, the bump shear strength of bare dies were decreased by HTST tests. In package, all the results of mechanical properties by multiple reflow test and HTST test were significantly lowered. It was shown that the adhesion between bump and die reduced obviously as tests going on. As for high temperature operational life test in the conditions of 150 °C and 320 mA (5040A∕cm2), the average stable service time of the package was 892 h, and the average ultimate service time of the package was 1053 h.

Failure Analysis of Advanced Microprocessors through Backside Approaches

1998 ◽  
Author(s):  
D. Davis ◽  
O. Diaz de Leon ◽  
L. Hughes ◽  
S. V. Pabbisetty ◽  
R. Parker ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Preparation Methods ◽  
Analysis Techniques ◽  
Analytical Approaches ◽  
Sample Preparation Methods ◽  
New Devices

Abstract The advent of Flip Chip and other complex package configurations and process technologies have made conventional failure analysis techniques inapplicable. This paper covers the ways in which conventional techniques have been modified to meet the FA challenges presented by these new devices – specifically, by forcing analysis to be done from the backside of the device. Modifications to the traditional FA process steps, including new sample preparation methods, changes in hardware, and alterations to physical failure analysis processes are described. To demonstrate the use of backside analytical approaches, some examples of applications and a case study are also included.

Localization of Dead Open in a Solder Bump by Space Domain Reflectometry

2012 ◽  
Author(s):  
David P. Vallett ◽  
Daniel A. Bader ◽  
Vladimir V. Talanov ◽  
Jan Gaudestad ◽  
Nicolas Gagliolo ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Failure Analysis ◽  
Quantum Interference ◽  
Flip Chip ◽  
Solder Bump ◽  
Frequency Range ◽  
Superconducting Quantum Interference Device ◽  
Space Domain ◽  
Non Destructive ◽  
The Magnetic Field

Abstract Space Domain Reflectometry (SDR) is a newly developed non-destructive failure analysis (FA) technique for localizing open defects in both packages and dies through mapping in space domain the magnetic field produced by a radio frequency (RF) current induced in the sample, herein the name Space Domain Reflectometry. The technique employs a scanning superconducting quantum interference device (SQUID) RF microscope operating over a frequency range from 60 to 200 MHz. In this paper we demonstrate that SDR is capable of locating defective micro bumps in a flip-chip device.

Fundamental Study on Adhesion of Epoxy Underfill Materials with Passivation Layer in Flip-chip Packaging

2001 ◽  
Vol 682 ◽  
Author(s):  
Shijian Luo ◽  
C. P. Wong
Keyword(s):  
High Temperature ◽  
Coupling Agent ◽  
Silane Coupling Agent ◽  
Flip Chip ◽  
Polymer Chains ◽  
Passivation Layer ◽  
High Humidity ◽  
Fundamental Study ◽  
Silane Coupling ◽  
Flip Chip Packaging

ABSTRACTThe influence of aging in an environment with a high temperature and a high humidity on the adhesion performance of underfill material (epoxy cured with acid anhydride) to the passivation layer in flip chip packaging is discussed. Adhesion of underfill to different passivation materials degrades after aging in a high temperature and high humidity environment. The extent of this degradation is dependent on the hydrophilicity of the passivation material. Hydrophilic passivation such as silicon oxide (SiO2) and silicon nitride (Si3N4) shows much more severe adhesion degradation than hydrophobic passivation such as benzocyclobutene (BCB) and polyimide (PI). The mobility of absorbed water and of polymer chains is studied with solid state nuclear magnetic resonance (NMR) spectroscopy. Higher mobility of absorbed water and of polymer chains in rubbery state polymers contributes to faster adhesion degradation during high temperature and high humidity aging. The adhesion stability of hydrophilic passivation can be successfully improved by use of a silane coupling agent that introduces stable chemical bond at interface. A flow micro-calorimeter was used to study the absorption of silane coupling agent onto glass surface. The difference in adhesion retention improvement between aminosilane and epoxysilane is discussed.

Flip Chip Packaging of Wafer Level Encapsulated RF MEMS Tunable Capacitors

2013 ◽  
Author(s):  
Shawn J. Cunningham ◽  
Yvonne Heng ◽  
Nabeel Idrisi ◽  
Brad Nelson ◽  
John McKillop
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Rf Mems ◽  
Temperature Cycling ◽  
Battery Life ◽  
Mems Devices ◽  
Wafer Level ◽  
Element Analysis ◽  
Tunable Capacitors ◽  
Flip Chip Packaging

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place. In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability. In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.

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