CMOS Backside Deprocessing With TMAH / IPA as a Sample Preparation Procedure for Failure Analysis

2002 ◽  
Author(s):  
Seth Prejean ◽  
Victoria Bruce ◽  
Joyce Burke
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Process Development ◽  
Future Research ◽  
Cmos Process ◽  
Preparation Technique ◽  
Root Cause ◽  
Sample Preparation Procedure ◽  
Root Cause Failure Analysis ◽  
Preparation Techniques

Abstract This paper is about a sample preparation technique that is based on a previous research publication1. The technique was initially used for the investigation of salicide formation for CMOS process development. The initial results were very good and proved to be helpful with root cause failure analysis. Once the technique proved to be a viable failure analysis (FA) tool, a research team was formed to continue the development. This paper is written in conjunction with this team. The team is presently focused on developing a repeatable and reliable methodology of deprocessing CMOS devices from the backside. The team is also developing a methodology for post deprocessing analysis once the backside silicon is removed. The research that is presented here focuses on packaged as well as unpackaged devices. Etch rates and selectivity of tetramethylammoniumhydroxide (TMAH) is investigated along with temperature dependencies. Package material and chemical interference issues were discovered and remedied with special preparation techniques. Post deprocessing analysis is considered and many ideas are proposed as part of future research.

Advanced TEM sample preparation techniques for submicron Si devices

1995 ◽  
Vol 53 ◽  
pp. 516-517 ◽  
Author(s):  
P. B. Basham ◽  
H. L. Tsai
Keyword(s):  
Sample Preparation ◽  
Process Development ◽  
Light Transmission ◽  
Specific Area ◽  
Turnaround Time ◽  
Small Hole ◽  
Area Of Interest ◽  
Transmission Electron ◽  
Polished Side ◽  
Preparation Techniques

The use of transmission electron microscopy (TEM) to support process development of advanced microelectronic devices is often challenged by a large amount of samples submitted from wafer fabrication areas and specific-spot analysis. Improving the TEM sample preparation techniques for a fast turnaround time is critical in order to provide a timely support for customers and improve the utilization of TEM. For the specific-area sample preparation, a technique which can be easily prepared with the least amount of effort is preferred. For these reasons, we have developed several techniques which have greatly facilitated the TEM sample preparation.For specific-area analysis, the use of a copper grid with a small hole is found to be very useful. With this small-hole grid technique, TEM sample preparation can be proceeded by well-established conventional methods. The sample is first polished to the area of interest, which is then carefully positioned inside the hole. This polished side is placed against the grid by epoxy Fig. 1 is an optical image of a TEM cross-section after dimpling to light transmission.

Novel Failure Analysis Sample Preparation Techniques for PoP Packaging

2012 ◽  
Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanisms ◽  
Preparation Process ◽  
Space Saving ◽  
Optical Probing ◽  
Preparation Techniques

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

Introduction of a Novel Sample Preparation Technique for the Failure Analysis of Silicon Integrated Photonics Modules

2019 ◽  
Author(s):  
Pradip Sairam Pichumani ◽  
Fauzia Khatkhatay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Silicon Photonics ◽  
Cmos Technology ◽  
Single Step ◽  
Oxide Semiconductor ◽  
Disruptive Technology ◽  
Preparation Technique ◽  
Test Vehicle ◽  
Sample Preparation Technique

Abstract Silicon photonics is a disruptive technology that aims for monolithic integration of photonic devices onto the complementary metal-oxide-semiconductor (CMOS) technology platform to enable low-cost high-volume manufacturing. Since the technology is still in the research and development phase, failure analysis plays an important role in determining the root cause of failures seen in test vehicle silicon photonics modules. The fragile nature of the test vehicle modules warrants the development of new sample preparation methods to facilitate subsequent non-destructive and destructive analysis methods. This work provides an example of a single step sample preparation technique that will reduce the turnaround time while simultaneously increasing the scope of analysis techniques.

The Novel TEM Sample Preparation Approach for Targeted via with Barrier/Cu Seed Layer Inspection

2009 ◽  
Author(s):  
Wen-Fei Hsieh ◽  
Shih-Hsiang Tseng ◽  
Bo Min She
Keyword(s):  
Sample Preparation ◽  
Cross Section ◽  
Seed Layer ◽  
Target Location ◽  
Process Development ◽  
Process Integration ◽  
Ion Beam ◽  
Main Tool ◽  
Dual Beam ◽  
Sample Preparation Procedure

Abstract In this study, an FIB-based cross section TEM sample preparation procedure for targeted via with barrier/Cu seed layer is introduced. The dual beam FIB with electron beam for target location and Ga ion beam for sample milling is the main tool for the targeted via with barrier/Cu seed layer inspection. With the help of the FIB operation and epoxy layer protection, ta cross section TEM sample at a targeted via with barrier/Cu seed layer could be made. Subsequent TEM inspection is used to verify the quality of the structure. This approach was used in the Cu process integration performance monitor. All these TEM results are very helpful in process development and yield improvement.

Sample Preparation Challenges In WLCSP Epoxy Underfill Coating Removal

2012 ◽  
Author(s):  
Jason H. Lagar ◽  
Rudolf A. Sia
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Vital Role ◽  
Fault Isolation ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Coating Removal ◽  
Customer Returns ◽  
Preparation Techniques ◽  
Mechanical Defect

Abstract Most Wafer Level Chip Scale Package (WLCSP) units returned by customers for failure analysis are mounted on PCB modules with an epoxy underfill coating. The biggest challenge in failure analysis is the sample preparation to remove the WLCSP device from the PCB without inducing any mechanical defect. This includes the removal of the underfill material to enable further electrical verification and fault isolation analysis. This paper discusses the evaluations conducted in establishing the WLCSP demounting process and removal of the epoxy underfill coating. Combinations of different sample preparation techniques and physical failure analysis steps were evaluated. The established process enabled the electrical verification, fault isolation and further destructive analysis of WLCSP customer returns mounted on PCB and with an epoxy underfill coating material. This paper will also showcase some actual full failure analysis of WLCSP customer returns where the established process played a vital role in finding the failure mechanism.

Cutting-Edge Sample Preparation from FIB to Ar Concentrated Ion Beam Milling of Advanced Semiconductor Devices

2020 ◽  
Author(s):  
C.S. Bonifacio ◽  
P. Nowakowski ◽  
R. Li ◽  
M.L. Ray ◽  
P.E. Fischione ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Devices ◽  
Specific Area ◽  
Cutting Edge ◽  
Preparation Technique ◽  
Ion Milling ◽  
Sample Preparation Technique

Abstract Fast and accurate examination from the bulk to the specific area of the defect in advanced semiconductor devices is critical in failure analysis. This work presents the use of Ar ion milling methods in combination with Ga focused ion beam (FIB) milling as a cutting-edge sample preparation technique from the bulk to specific areas by FIB lift-out without sample-preparation-induced artifacts. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 15 nm are obtained.

Comparison of Precision XTEM Specimen Preparation Techniques for Semiconductor Failure Analysis

1997 ◽  
Vol 3 (S2) ◽  
pp. 357-358
Author(s):  
C. Amy Hunt
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Mechanical Polishing ◽  
Specimen Preparation ◽  
Ion Milling ◽  
Tem Analysis ◽  
The Past ◽  
Preparation Techniques

The demand for TEM analysis in semiconductor failure analysis is rising sharply due to the shrinking size of devices. A well-prepared sample is a necessity for getting meaningful results. In the past decades, a significant amount of effort has been invested in improving sample preparation techniques for TEM specimens, especially precision cross-sectioning techniques. The most common methods of preparation are mechanical dimpling & ion milling, focused ion beam milling (FIBXTEM), and wedge mechanical polishing. Each precision XTEM technique has important advantages and limitations that must be considered for each sample.The concept for both dimpling & ion milling and wedge specimen preparation techniques is similar. Both techniques utilize mechanical polishing to remove the majority of the unwanted material, followed by ion milling to assist in final polishing or cleaning. Dimpling & ion milling produces the highest quality samples and is a relatively easy technique to master.

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