Root Cause Analyses of Metal Bridging for Copper Damascene Process

2005 ◽  
Author(s):  
Z. G. Song ◽  
S. P. Neo ◽  
S. K. Loh ◽  
C. K. Oh
Keyword(s):  
Failure Mechanisms ◽  
Copper Corrosion ◽  
Microelectronic Device ◽  
Root Cause ◽  
Damascene Process ◽  
New Process ◽  
Copper Cmp

Abstract New process will introduce new failure mechanisms during microelectronic device manufacturing. Even if the same defect, its root causes can be different for different processes. For aluminum(Al)-tungsten(W) metallization, the root cause of metal bridging is quite simple and mostly it is blocked etch or under-etch. But, for copper damascene process, the root causes of metal bridging are complicated. This paper has discussed the various root causes of metal bridging for copper damascene process, such as those related to litho-etch issue, copper CMP issue, copper corrosion issue and so on.

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

1996 ◽  
Author(s):  
E. Widener ◽  
S. Tatti ◽  
P. Schani ◽  
S. Crown ◽  
B. Dunnigan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Product Quality ◽  
Cmos Process ◽  
Designed Experiments ◽  
Root Cause ◽  
Poly Silicon ◽  
New Process ◽  
Supply Current ◽  
Electrical Analysis ◽  
Current Characteristics

Abstract A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

Applications of Focused Ion Beam Technology in Bonding Failure Analysis for Microelectronic Devices

2011 ◽  
Vol 58-60 ◽  
pp. 2171-2176 ◽  
Author(s):  
Yuan Chen ◽  
Xiao Wen Zhang
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Failure Mechanisms ◽  
Microelectronic Device ◽  
Mechanism Study ◽  
Basic Principles ◽  
The Past ◽  
Microelectronic Devices ◽  
Bonding Failure

Focused ion beam (FIB) system is a powerful microfabrication tool which uses electronic lenses to focus the ion beam even up to nanometer level. The FIB technology has become one of the most necessary failure analysis and failure mechanism study tools for microelectronic device in the past several years. Bonding failure is one of the most common failure mechanisms for microelectronic devices. But because of the invisibility of the bonding interface, it is difficult to analyze this kind of failure. The paper introduced the basic principles of FIB technology. And two cases for microelectronic devices bonding failure were analyzed successfully by FIB technology in this paper.

Strategies to Address Low DPPM Failure Mechanisms on Automotive Grade Wi-Fi Radio Frequency Devices

2015 ◽  
Author(s):  
Kai Wang ◽  
Sadia Lone ◽  
Colin Thomas ◽  
Rhys Weaver
Keyword(s):  
Failure Analysis ◽  
Continuous Improvement ◽  
Failure Mechanisms ◽  
Time Frame ◽  
Cause Analysis ◽  
Automotive Market ◽  
Root Cause ◽  
Rigorous Testing ◽  
Additional Demand

Abstract System suppliers in the automotive market have an expectation that their IC suppliers provide products with low defective parts per million (DPPM) and have methodologies in place to drive towards 0ppm (Zero Parts Per Million). IC suppliers to the automotive market have supply chains and test methodologies in place to achieve such low DPPMs, but the systems suppliers will still require root cause analysis on every failure. The IC supplier is expected to demonstrate a containment, corrective action and continuous improvement in a very tight time frame. This additional demand of automotive customers poses a challenge to the quality of IC devices and the concept of cross departmental failure analysis. In this paper, we look at a complex Wi-Fi design with multiple IEEE specific radios, and how to address the few parts that escape the rigorous testing by IC supplier to improve the quality for the automotive IC.

An Application of Breakthrough Failure Analysis Techniques in Eliminating Silicon Dislocation Problem in Sub-Micron CMOS Devices

1997 ◽  
Author(s):  
E. H. Yeoh ◽  
W. M. Mak ◽  
H. C. Lock ◽  
S. K. Sim ◽  
C. C. Ooi ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Packing Density ◽  
Failure Mechanisms ◽  
Potential Solution ◽  
Critical Dimensions ◽  
Functional Failure ◽  
Analysis Techniques ◽  
Root Cause ◽  
First Time

Abstract As device interconnect layers increase and transistor critical dimensions decrease below sub-micron to cater for higher speed and higher packing density, various new and subtle failure mechanisms have emerged and are becoming increasingly prevalent. Silicon dislocation is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre GFA wafer' functional failure problem. In this paper, several breakthrough failure analysis techniques used to narrow down and identify this new mechanism will be presented. Root cause determination and potential solution to this problem will also be discussed.

Applications of Multi-Variate Statistical Analysis of Spectrum Images to Microelectronic Devices

2001 ◽  
Vol 7 (S2) ◽  
pp. 1158-1159
Author(s):  
J. Bruley
Keyword(s):  
Quantitative Information ◽  
Atomic Resolution ◽  
Metal Silicide ◽  
Microelectronic Device ◽  
Interfacial Chemistry ◽  
Electrical Failure ◽  
Root Cause ◽  
Microelectronic Devices ◽  
Software Packages ◽  
Scattering Effects

It is not uncommon for an electrical failure in a microelectronic device to be traced back to an individual resistive contact, such as a W contact lined by TiN to the underlying metal silicide [1]. Identifying the root cause of the defective cell then requires the capability of extracting interfacial chemistry and microstructure with near atomic resolution, which is achieved by recording EELS and EDX data either along 1-d lines or from 2-d arrays. EELS data are characterized by intrinsically low signal-to-background ratios and plural inelastic-scattering effects, which presents a challenge to the reliability of the methods used to extract quantitative information from a spectrum image. Commercially available software packages by Emispec and Gatan currently provide routines for power-law or polynomial background fits and allow the net counts under peaks or edges to be determined from each pixel. in both cases each spectrum in the series is processed in the same manner.

scholarly journals Failure investigation as a route to improving integrity of titanium alloys in service

2020 ◽  
Vol 321 ◽  
pp. 04007
Author(s):  
C. Collins ◽  
F.F. Dear ◽  
D. Rugg ◽  
D. Dye
Keyword(s):  
Titanium Alloy ◽  
Titanium Alloys ◽  
Feedback Loop ◽  
State Of The Art ◽  
Failure Mechanisms ◽  
Damage And Failure ◽  
Root Cause ◽  
Aerospace Applications ◽  
Failure Investigation ◽  
Comprehensive Framework

Increasing demands on titanium alloys in aerospace applications have driven a push towards deeper understanding of their behaviour in service. This extends from component performance during planned operation to damage mechanisms and how parts may ultimately fail. Investigation of damage and failure requires a comprehensive framework of techniques in order to identify a root cause, and further the understanding of failure mechanisms. It is crucial to defining and improving component lifetimes via a design optimisation feedback loop. This paper presents an overview of the techniques used in state-of-the-art industrial titanium alloy failure investigation, highlighting the inherent reciprocal links to frontline research and the need for constant innovation.

Poly Undercut Induced Device Asymmetric Failure

2016 ◽  
Author(s):  
Wen Hui Wang ◽  
Mei Chuang Lin ◽  
Shiuan Wen Huang
Keyword(s):  
High Resistance ◽  
Failure Mechanisms ◽  
Failure Type ◽  
Root Cause ◽  
Defect Location ◽  
Soft Failure ◽  
Current Feature ◽  
Current Difference

Abstract Device asymmetric current is a common soft failure type in real nano-probing cases. Generally speaking, it is not easy to find out the root cause. LDD shadowing, Poly depletion are well known failure mechanisms causing asymmetric current due to an equivalent high resistance at defect location. Based on the defect serious condition, even some hard defect like channel AA pitting will show the similar I-V feature with previous 2 soft fail cases. This paper will introduce another type of asymmetric current feature – poly bottom undercut which I-V curve still keeps ideal linear and saturation area, but the asymmetric current difference is obvious.

SMT Ceramic Capacitor Failure Mechanisms, Isolation Tools, Techniques and Analysis Methods

2000 ◽  
Author(s):  
Ralph A. Carbone ◽  
David J. Roche
Keyword(s):  
Failure Mechanisms ◽  
Mechanical Damage ◽  
Acoustic Microscopy ◽  
Root Cause ◽  
Successful Isolation ◽  
Ceramic Capacitor ◽  
Ceramic Capacitors ◽  
Cause Of Failure ◽  
Electronic Parts ◽  
Tools And Techniques

Abstract Surface Mount Technology (SMT) ceramic capacitors are widely used on virtually every type of electronic product. In computer systems, SMT capacitors populate the majority of electronic parts found on each Printed Circuit Assembly (PCA) within the product, primarily as bypass or coupling devices between power and ground. As such, the opportunity for failure is substantially higher than with other commonly used active or passive components. Additionally, the relatively small ceramic bodies are prone to mechanical damage. Their proportionately high numbers, sensitivity to mechanical stress and difficulty in isolating to a specific failing device on the PCA (since many of these parts are in parallel with many other identical capacitors) all combine to make the successful isolation and analysis of the root cause of failure particularly difficult for the failure analyst. Often, the cause of failure is misdiagnosed, or the evidence is compromised by the methods used to perform the analysis. This paper will discuss the common failure mechanisms associated with SMT ceramic capacitors, as well as some innovative non-destructive isolation tools and techniques, including C-Mode Scanning Acoustic Microscopy (C-SAM), Infrared thermography (IR) and Micro-Focus X-ray analysis. Several case studies will be cited which demonstrate each of the mechanisms and methods. Additionally, the processes used to properly analyze these defects will be examined.

Analysis of Power MOSFET Active Temperature Cycling Failures

2013 ◽  
Author(s):  
Ian Kearney
Keyword(s):  
Development Process ◽  
Failure Mechanisms ◽  
Temperature Cycling ◽  
Power Devices ◽  
Contributing Factors ◽  
Power Mosfet ◽  
Root Cause ◽  
Power Cycling ◽  
Performance Deterioration ◽  
And Performance

Abstract Performance degradation due to fatigue accumulation from the repetitive switching of high load current is critical to understanding robust power MOSFET product design. In this paper, we present a novel high-current-temperature (HCT) characterization system used to investigate real world powercycling failure mechanisms. The effects of electric current Joule heating, non-uniform temperature distribution and performance deterioration of discrete power devices are discussed. Thermal fatigue of solder joints and thick aluminum wire bonding are common weak spots with regard to power-cycling capability. We report performance failure mechanisms and discuss the superposition of contributing factors in defining root cause. Results discuss various package influences as part of a robust power MOSFET development process.

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