Applications of Focused Ion Beam Technology in Bonding Failure Analysis for Microelectronic Devices

2011 ◽  
Vol 58-60 ◽  
pp. 2171-2176 ◽  
Author(s):  
Yuan Chen ◽  
Xiao Wen Zhang
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Failure Mechanisms ◽  
Microelectronic Device ◽  
Mechanism Study ◽  
Basic Principles ◽  
The Past ◽  
Microelectronic Devices ◽  
Bonding Failure

Focused ion beam (FIB) system is a powerful microfabrication tool which uses electronic lenses to focus the ion beam even up to nanometer level. The FIB technology has become one of the most necessary failure analysis and failure mechanism study tools for microelectronic device in the past several years. Bonding failure is one of the most common failure mechanisms for microelectronic devices. But because of the invisibility of the bonding interface, it is difficult to analyze this kind of failure. The paper introduced the basic principles of FIB technology. And two cases for microelectronic devices bonding failure were analyzed successfully by FIB technology in this paper.

Layout Overlay Techniques to Improve Failure Analysis

1998 ◽  
Author(s):  
Christian Burmer ◽  
Siegfried Görlich ◽  
Siegfried Pauthner
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
New Technologies ◽  
Ion Beam ◽  
Image Correlation ◽  
Microelectronic Devices ◽  
Overlay Technique ◽  
Correlation Techniques ◽  
Navigation Software ◽  
Image Format

Abstract New layout overlay technique has been developed based on standard image correlation techniques to support failure analysis in modern microelectronic devices, which are critical to analyze because they are realized in new technologies using sub-ìm design rules, chemical mechanical polishing techniques (CMP) and autorouted design techniques. As the new technique is realized as an extension of a standard CAD-navigation software and as it makes use of standard image format "TIFF" for data input, which is available at all modern equipments for failure analysis, these technique can be applied to all modern failure analysis methods. Here examples are given for three areas of application: circuit modification using Focused Ion Beam (FIB), support of preparation for backside inspection and fault localization using emission microscopy.

Comparison of Precision XTEM Specimen Preparation Techniques for Semiconductor Failure Analysis

1997 ◽  
Vol 3 (S2) ◽  
pp. 357-358
Author(s):  
C. Amy Hunt
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Mechanical Polishing ◽  
Specimen Preparation ◽  
Ion Milling ◽  
Tem Analysis ◽  
The Past ◽  
Preparation Techniques

The demand for TEM analysis in semiconductor failure analysis is rising sharply due to the shrinking size of devices. A well-prepared sample is a necessity for getting meaningful results. In the past decades, a significant amount of effort has been invested in improving sample preparation techniques for TEM specimens, especially precision cross-sectioning techniques. The most common methods of preparation are mechanical dimpling & ion milling, focused ion beam milling (FIBXTEM), and wedge mechanical polishing. Each precision XTEM technique has important advantages and limitations that must be considered for each sample.The concept for both dimpling & ion milling and wedge specimen preparation techniques is similar. Both techniques utilize mechanical polishing to remove the majority of the unwanted material, followed by ion milling to assist in final polishing or cleaning. Dimpling & ion milling produces the highest quality samples and is a relatively easy technique to master.

Direct Imaging of Device Characteristics In a Focused ion Beam System

1998 ◽  
Vol 4 (S2) ◽  
pp. 652-653 ◽  
Author(s):  
A. N. Campbell ◽  
J. M. Soden
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Cross Sections ◽  
Material Removal ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Yield Enhancement ◽  
The Past ◽  
Design Changes ◽  
Design Debugging

A great deal can be learned about integrated circuits (ICs) and microelectronic structures simply by imaging them in a focused ion beam (FIB) system. FIB systems have evolved during the past decade from something of a curiosity to absolutely essential tools for microelectronics design verification and failure analysis. FIB system capabilities include localized material removal, localized deposition of conductors and insulators, and imaging. A major commercial driver for FIB systems is their usefulness in the design debugging cycle by (1) rewiring ICs quickly to test design changes and (2) making connection to deep conductors to facilitate electrical probing of complex ICs. FIB milling is also used for making precision cross sections and for TEM sample preparation of microelectronic structures for failure analysis and yield enhancement applications.

Failure Analysis of Flip Chip C4 Package Using Focused Ion Beam Milling Technique

2011 ◽  
Author(s):  
Lihong Cao ◽  
Loc Tran ◽  
Wallace Donna
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Sections ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Failure Mechanisms ◽  
Organic Substrate ◽  
Dual Beam ◽  
Preparation Techniques

Abstract This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. Dual- Beam Focused Ion Beam (DB FIB) cross sections were successful in detecting failure mechanisms related either to the die/C4 bump or package defect inside the organic substrate. This paper outlines detailed sample preparation techniques prior to performing the DB FIB cross-sections, along with case studies of DB FIB cross-sections.

Advances in Large-Area Microelectronic Device Deprocessing for Physical Failure Analyses and Quality Control

2018 ◽  
Author(s):  
Pawel Nowakowski ◽  
Michael Boccabella ◽  
Mary Ray ◽  
Paul Fischione
Keyword(s):  
Quality Control ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Semiconductor Device ◽  
Ion Beam ◽  
Layer By Layer ◽  
Microelectronic Device ◽  
Large Area ◽  
Microelectronic Devices ◽  
Development Failure

Abstract Focused ion beam (FIB) techniques are often used when delayering semiconductor devices. However, using FIB technology for device delayering has limitations. One of these limitations prevents the exposure of a large slope area on the sample, which reveals all layers simultaneously. The delayering process is complex and requires prior process knowledge, such as cross-section architecture, composition, and layer uniformity. This paper discusses advances in semiconductor device deprocessing for product development, failure analysis, and quality control using low-energy, argon broad ion beam (BIB) milling. Ar BIB milling is a practical solution for accurate delayering of advanced microelectronic devices. Results of the spot milling of a whole 300 mm wafer experiment and top-down delayering of wafer pieces experiment show that successful device delayering can be achieved by either spot milling or layer-by-layer milling. These two strategies are easily achieved, for either small wafer pieces or full 300 mm wafer investigation.

Fluorocarbon Precursor for High Aspect Ratio via Milling in Focused Ion Beam Modification of Integrated Circuits

2004 ◽  
Author(s):  
Valery Ray
Keyword(s):  
Side Effects ◽  
Aspect Ratio ◽  
Integrated Circuits ◽  
High Aspect Ratio ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Enabling Technology ◽  
Si Substrate ◽  
Ion Beam Modification ◽  
The Past

Abstract Gas Assisted Etching (GAE) is the enabling technology for High Aspect Ratio (HAR) circuit access via milling in Focused Ion Beam (FIB) circuit modification. Metal interconnect layers of microelectronic Integrated Circuits (ICs) are separated by Inter-Layer Dielectric (ILD) materials, therefore HAR vias are typically milled in dielectrics. Most of the etching precursor gases presently available for GAE of dielectrics on commercial FIB systems, such as XeF2, Cl2, etc., are also effective etch enhancers for either Si, or/and some of the metals used in ICs. Therefore use of these precursors for via milling in dielectrics may lead to unwanted side effects, especially in a backside circuit edit approach. Making contacts to the polysilicon lines with traditional GAE precursors could also be difficult, if not impossible. Some of these precursors have a tendency to produce isotropic vias, especially in Si. It has been proposed in the past to use fluorocarbon gases as precursors for the FIB milling of dielectrics. Preliminary experimental evaluation of Trifluoroacetic (Perfluoroacetic) Acid (TFA, CF3COOH) as a possible etching precursor for the HAR via milling in the application to FIB modification of ICs demonstrated that highly enhanced anisotropic milling of SiO2 in HAR vias is possible. A via with 9:1 aspect ratio was milled with accurate endpoint on Si and without apparent damage to the underlying Si substrate.

Direct Plan View FIB Liftout for Near-Surface Defect Analysis in TEM

2013 ◽  
Author(s):  
Max L. Lifson ◽  
Carla M. Chapman ◽  
D. Philip Pokrinchak ◽  
Phyllis J. Campbell ◽  
Greg S. Chrisman ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Silicon Germanium ◽  
Focused Ion Beam ◽  
Surface Defects ◽  
Ion Beam ◽  
Misfit Dislocations ◽  
Tem Analysis ◽  
Plan View ◽  
Near Surface ◽  
Straightforward Method

Abstract Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.

Fast Turn-around Failure Analysis of Metal Interconnection Using FIB and LA ICP-MS

2010 ◽  
Author(s):  
Zixiao Pan ◽  
Wei Wei ◽  
Fuhe Li
Keyword(s):  
Failure Analysis ◽  
Inductively Coupled Plasma ◽  
Structural Damage ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Detection Sensitivity ◽  
Chemical Contamination ◽  
Inductively Coupled ◽  
Minimal Sample ◽  
Icp Ms

Abstract This paper introduces our effort in failure analysis of a 200 nm thick metal interconnection on a glass substrate and covered with a passivation layer. Structural damage in localized areas of the metal interconnections was observed with the aid of focused ion beam (FIB) cross-sectioning. Laser ablation inductively coupled plasma mass spectroscopy (LA ICP-MS) was then applied to the problematic areas on the interconnection for chemical survey. LA ICP-MS showed direct evidence of localized chemical contamination, which has likely led to corrosion (or over-etching) of the metal interconnection and the assembly failure. Due to the high detection sensitivity of LA ICP-MS and its compatibility with insulating material analysis, minimal sample preparation is required. As a result, the combination of FIB and LA ICP-MS enabled successful meso-scale failure analysis with fast turnaround and reasonable cost.

Logical-to-Physical Device Navigation using Place-and-Route Data as an Alternative to LVS

2006 ◽  
Author(s):  
Roger Nicholson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Traditional Methods ◽  
Navigation Data ◽  
Use Of Time ◽  
Place And Route ◽  
Physical Layout

Abstract Logical-to-physical device navigation for failure analysis is often used to drive physical probers and focused ion beam tools. Traditional methods of creating navigation data rely upon the use of time consuming Layout-versus-Schematic (LVS) based methods. By using existing place-and-route data, full cross-linked navigation between schematic and physical layout may be achieved in a fraction of the time that it takes for the LVS methods to be used. Place-and-route data offers significantly more information to the analyst than LVS based data.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

Sign in / Sign up

Export Citation Format

Share Document