Novel Sample Preparation Technique for Backside Analysis of Singulated Die

Abstract A case study of a transient induced latch-up (TLU) problem is presented, which was identified during the development of a 60 V, 0.8 µm BiCMOS power control device. The mechanism was characterized by controlled transient latch-up testing and found to be fairly unusual, being triggered by a fast decreasing not necessarily negative spike or glitch on the positive supply pin. Emission Microscopy (EMMI) and Transient Interferometric Mapping (TIM) successfully located the parasitic silicon controlled rectifiers (SCR) structure. TIM is an infra-red laser beam based technique for back side analysis. TIM analysis enables concurrent imaging of carrier injection and heating in nanosecond timescale providing more detailed information on the SCR action than more often used static photon emission or dynamic TLP / PICA imaging.

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Selective Etching of Heavily-Boron-Doped Si Substrate Using Lightly-Boron-Doped Si Epi as an Etch Stop Layer

ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2015p0306 ◽

2015 ◽

Author(s):

Valentina Korchnoy

Keyword(s):

Sample Preparation ◽

Preparation Technique ◽

Back Side ◽

Flip Chips ◽

Boron Doped ◽

Sample Preparation Technique ◽

Etch Stop ◽

Etch Stop Layer ◽

Optical Probing ◽

Wet Etch

Abstract A sample preparation technique for flip chips (FC) deprocessing from the back side proposed. The technique uses HNA chemistry (consisting of a mixture of acids: hydrofluoric, nitric and acetic) to wet-etch the heavily-boron-doped Si bulk substrate selectively to the lightly-boron-doped Si epi. The procedure can be used as a FC device sample preparation technique for back-side optical probing and FIB editing.

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Fast and Effective Sample Preparation Technique for Backside Fault Isolation on GaN Packaged Devices

10.31399/asm.cp.istfa2021p0279 ◽

2021 ◽

Author(s):

Tony Colpaert ◽

Stefaan Verleye

Keyword(s):

Sample Preparation ◽

Focused Ion Beam ◽

Ion Beam ◽

Photon Emission ◽

Fault Isolation ◽

Preparation Technique ◽

Laser Marking ◽

Sample Preparation Technique ◽

P Type ◽

Metal Layers

Abstract This paper describes a fast and effective sample preparation method to allow backside fault localization on GaN package devices. Backside analysis by Photon Emission Microscopy (PEM) is becoming preferable to frontside analysis when the die is covered by metal layers. This paper describes an optimized method for backside sample preparation on GaN package devices having a thick heavily doped p-type silicon substrate. The method combines mechanical and chemical deprocessing steps, resulting in a fast and effective sample preparation technique for PEM analysis. Additionally, the laser marking process parameters to facilitate orientation during the final physical failure analysis by Focused Ion Beam (FIB) are also shared.

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SEM evaluation of the TEM cold-stage double-film specimen

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100111471 ◽

1984 ◽

Vol 42 ◽

pp. 272-273

Author(s):

Jayesh Bellare

Keyword(s):

Spatial Distribution ◽

Sample Preparation ◽

Sample Thickness ◽

Specimen Preparation ◽

Preparation Technique ◽

Liquid Sample ◽

Thin Specimen ◽

Sample Preparation Technique ◽

Cold Stage ◽

Film Specimen

Seeing is believing, but only after the sample preparation technique has received a systematic study and a full record is made of the treatment the sample gets.For microstructured liquids and suspensions, fast-freeze thermal fixation and cold-stage microscopy is perhaps the least artifact-laden technique. In the double-film specimen preparation technique, a layer of liquid sample is trapped between 100- and 400-mesh polymer (polyimide, PI) coated grids. Blotting against filter paper drains excess liquid and provides a thin specimen, which is fast-frozen by plunging into liquid nitrogen. This frozen sandwich (Fig. 1) is mounted in a cooling holder and viewed in TEM.Though extremely promising for visualization of liquid microstructures, this double-film technique suffers from a) ireproducibility and nonuniformity of sample thickness, b) low yield of imageable grid squares and c) nonuniform spatial distribution of particulates, which results in fewer being imaged.

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Direct structure images of 30° partial dislocation cores in silicon

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100126111 ◽

1987 ◽

Vol 45 ◽

pp. 242-243

Author(s):

J. C. Barry ◽

H. Alexander

Keyword(s):

Dislocation Core ◽

Preparation Technique ◽

Burgers Vector ◽

Vector Type ◽

Sample Preparation Technique ◽

Lattice Images ◽

Dislocation Core Structure ◽

Type Lattice ◽

Direct Inspection

Dislocations in silicon produced by plastic deformation are generally dissociated into partials. 60° dislocations (Burgers vector type 1/2[101]) are dissociated into 30°(Burgers vector type 1/6[211]) and 90°(Burgers vector type 1/6[112]) dislocations. The 30° partials may be either of “glide” or “shuffle” type. Lattice images of the 30° dislocation have been obtained with a JEM 100B, and with a JEM 200Cx. In the aforementioned experiments a reasonable but imperfect match was obtained with calculated images for the “glide” model. In the present experiment direct structure images of 30° dislocation cores have been obtained with a JEOL 4000EX. It is possible to deduce the 30° dislocation core structure by direct inspection of the images. Dislocations were produced by compression of single crystal Si (sample preparation technique described in Alexander et al.).

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Dynamic Photon Emission on FinFET Devices Through Novel Scan Test Approaches

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0160 ◽

2019 ◽

Author(s):

Ranganathan Gopinath ◽

Ravikumar Venkat Krishnan ◽

Lua Winson ◽

Phoa Angeline ◽

Jin Jie

Keyword(s):

Test Pattern ◽

Photon Emission ◽

Pattern Generator ◽

Lower Probability ◽

Automated Test Equipment ◽

Use Patterns ◽

Infra Red ◽

Automatic Test Pattern Generator ◽

Technology Nodes ◽

Established Technique

Abstract Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

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Case Study in Fault Isolation of a Metal Short for Yield Enhancement

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0049 ◽

2010 ◽

Author(s):

Sarven Ipek ◽

David Grosjean

Keyword(s):

Failure Analysis ◽

Failure Mechanism ◽

Photon Emission ◽

Fault Isolation ◽

Yield Enhancement ◽

Analysis Technique ◽

Laser Signal ◽

Signal Injection ◽

Microscopy Techniques

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.

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Introduction of a Novel Sample Preparation Technique for the Failure Analysis of Silicon Integrated Photonics Modules

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0508 ◽

2019 ◽

Author(s):

Pradip Sairam Pichumani ◽

Fauzia Khatkhatay

Keyword(s):

Sample Preparation ◽

Failure Analysis ◽

Silicon Photonics ◽

Cmos Technology ◽

Single Step ◽

Oxide Semiconductor ◽

Disruptive Technology ◽

Preparation Technique ◽

Test Vehicle ◽

Sample Preparation Technique

Abstract Silicon photonics is a disruptive technology that aims for monolithic integration of photonic devices onto the complementary metal-oxide-semiconductor (CMOS) technology platform to enable low-cost high-volume manufacturing. Since the technology is still in the research and development phase, failure analysis plays an important role in determining the root cause of failures seen in test vehicle silicon photonics modules. The fragile nature of the test vehicle modules warrants the development of new sample preparation methods to facilitate subsequent non-destructive and destructive analysis methods. This work provides an example of a single step sample preparation technique that will reduce the turnaround time while simultaneously increasing the scope of analysis techniques.

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A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0172 ◽

2007 ◽

Author(s):

Hung-Sung Lin ◽

Ying-Chin Hou ◽

Juimei Fu ◽

Mong-Sheng Wu ◽

Vincent Huang ◽

...

Keyword(s):

Liquid Crystal ◽

Circuit Design ◽

Process Design ◽

Integrated Circuit ◽

Photon Emission ◽

Integrated Circuit Design ◽

Nano Scale ◽

Leakage Path ◽

Related Defect

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

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