Application of the Infrared Microscope (IREM1) for Flip-Chip (C4) Failure Analysis

1999 ◽  
Author(s):  
A. N. Zaplatin ◽  
F. J. Low ◽  
Steve Seidel ◽  
Valluri R. Rao ◽  
T. H. Loh
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
Flip Chip ◽  
Hot Spot ◽  
Spectral Response ◽  
Real Life ◽  
Fault Isolation ◽  
Front Side ◽  
Process Technology ◽  
Ir Emission

Abstract Today’s process technology requires ever-increasing number of metal layers to meet the power and layout needs of modern products. These advances have rendered many of the conventional fault isolation (FI) methods from the front side of the die obsolete. The flip-chip package not only brings about the need to localize defects at die level through the Si substrate, but also introduces the need to isolate new defects at the package level. Recently, an infrared (IR) emission microscope which utilizes the cryogenically cooled HgCdTe (MCT) imaging array having spectral response of 0.8μm- 2.5μm, for near IR emission detection was developed. This system supersedes the conventional CCD based emission microscope with a spectral response of 0.4 μm-1.1μm. Since spectral detection extends into the thermal spectral region, it also offers an added advantage of detecting thermal spots on the die and flip-chip package where liquid crystal hot spot detection method is not possible. This article is an account of the use of the Mercury-Cadmium- Telluride based IR detector for “real life” failures. The article will demonstrate key features of the system as well as several FI examples. Both emission and thermal detection modes will be discussed. The authors will present several problems, including melted die bumps and package copper trace shorts, that could not be detected through conventional failure analysis (FA) methods, such as liquid crystal or front side emission microscopy. The MCT detectors increased sensitivity and backside navigation capabilities coupled with backside die preparation has proven itself an indispensable FA tool in the high volume manufacturing environment.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Extending Acoustic Microscopy for Comprehensive Failure Analysis Applications

2010 ◽  
Author(s):  
Sebastian Brand ◽  
Matthias Petzold ◽  
Peter Czurratis ◽  
Peter Hoffrogge
Keyword(s):  
Image Processing ◽  
Failure Analysis ◽  
Signal Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Acoustic Microscopy ◽  
Specific Information ◽  
Full Potential ◽  
Time Frequency ◽  
Non Destructive

Abstract In industrial manufacturing of microelectronic components, non-destructive failure analysis methods are required for either quality control or for providing a rapid fault isolation and defect localization prior to detailed investigations requiring target preparation. Scanning acoustic microscopy (SAM) is a powerful tool enabling the inspection of internal structures in optically opaque materials non-destructively. In addition, depth specific information can be employed for two- and three-dimensional internal imaging without the need of time consuming tomographic scan procedures. The resolution achievable by acoustic microscopy is depending on parameters of both the test equipment and the sample under investigation. However, if applying acoustic microscopy for pure intensity imaging most of its potential remains unused. The aim of the current work was the development of a comprehensive analysis toolbox for extending the application of SAM by employing its full potential. Thus, typical case examples representing different fields of application were considered ranging from high density interconnect flip-chip devices over wafer-bonded components to solder tape connectors of a photovoltaic (PV) solar panel. The progress achieved during this work can be split into three categories: Signal Analysis and Parametric Imaging (SA-PI), Signal Analysis and Defect Evaluation (SA-DE) and Image Processing and Resolution Enhancement (IP-RE). Data acquisition was performed using a commercially available scanning acoustic microscope equipped with several ultrasonic transducers covering the frequency range from 15 MHz to 175 MHz. The acoustic data recorded were subjected to sophisticated algorithms operating in time-, frequency- and spatial domain for performing signal- and image analysis. In all three of the presented applications acoustic microscopy combined with signal- and image processing algorithms proved to be a powerful tool for non-destructive inspection.

A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

2014 ◽  
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Localization ◽  
Cost Effective ◽  
Fault Isolation ◽  
Voltage Contrast ◽  
Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

Infra-Red Reflectance Microscopy (IRRM) for Daisy Chain Flip Chip Device Failure Analysis

2004 ◽  
Author(s):  
Carlo Grilletto ◽  
Steve Hsiung ◽  
Andrew Komrowski ◽  
John Soopikian ◽  
Daniel J.D. Sullivan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
State Of The Art ◽  
Failure Mechanisms ◽  
Simple Metal ◽  
X Ray ◽  
Infra Red ◽  
Cause Of Failure ◽  
Reflectance Microscopy ◽  
Ir Emission

Abstract This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.

Lock-in Thermography for Flip-Chip Package Failure Analysis

2012 ◽  
Author(s):  
Lihong Cao ◽  
Manasa Venkata ◽  
Jeffery Huynh ◽  
Joseph Tan ◽  
Meng-Yeow Tay ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Case Studies ◽  
Flip Chip ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Lock In

Abstract This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.

Cavity Up and Stack Die Backside Failure Analysis for Thin Die and High Pin Count Devices

2004 ◽  
Author(s):  
Dat Nguyen ◽  
Thao To ◽  
Ray Harrison ◽  
Cuong Phan ◽  
John Drummond
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Front Side ◽  
Defect Identification ◽  
Automated Test Equipment ◽  
Special Analysis ◽  
Failure Correlation ◽  
Similar Sample

Abstract Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.

Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis

2003 ◽  
Author(s):  
Seth J. Prejean ◽  
Joseph Shannon
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Easy Access ◽  
Induced Voltage ◽  
Emission Analysis ◽  
Defect Localization ◽  
Soi Devices

Abstract This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.

Characterization and Failure Analysis of 3D Integrated Semiconductor Devices—Novel Tools for Fault Isolation, Target Preparation and High Resolution Material Analysis

2010 ◽  
Author(s):  
Frank Altmann ◽  
Matthias Petzold ◽  
Christian Schmidt ◽  
Roland Salzer ◽  
Cathal Cassidy ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
High Rate ◽  
Target Preparation ◽  
Integrated Devices ◽  
Analysis Workflow ◽  
Silicon Vias

Abstract In this paper we will introduce novel methodical approaches for material and failure analysis of 3D integrated devices. The potential and advantages of the new concepts and tools will be demonstrated for flip-chip-like interconnects but in addition, for the first time, for Through Silicon Vias (TSV). The employed techniques combine non-destructive fault localization with efficient and accurate target preparation to get access for following microstructure diagnostics, forming a subsequent failure analysis workflow. The concept presented here involves the application of improved Lock-In Thermography (LIT), and three different innovative concepts of high rate Focused Ion Beam (FIB) techniques.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Infrared Thermography Developments for III-V Transistors and MMICs

2011 ◽  
Author(s):  
Dominique Carisetti ◽  
Mohsine Bouya ◽  
Odile Bezencenet ◽  
Bernard Servet ◽  
Jean-Claude Clément ◽  
...  
Keyword(s):  
Liquid Crystal ◽  
Failure Analysis ◽  
Infrared Thermography ◽  
Hot Spot ◽  
Ir Thermography ◽  
Thermal Measurement ◽  
Metal Insulator ◽  
Spot Detection ◽  
Metal Insulator Metal ◽  
Thermal Measurements

Abstract This paper focuses on infrared (IR) thermography capabilities on III-V components for thermal measurements applications and failure analysis (FA). The first part discusses the thermal mapping on InGaAs/AlGaAs PHEMT structure and compares IR thermal measurement with the well-known techniques as Raman and SThM. The second part discusses IR thermography on challenging FA for hot spot detection on the most popular type of capacitor for III-V MMICs as the metal-insulator-metal capacitor. It shows how IR thermography can easily localize very small pinholes in SiN, where liquid crystal and OBIRCH techniques are not well adapted.

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