New Front Side Access Approach for Low-k Dielectric/Cu Technologies in Plastic Package

2011 ◽  
Author(s):  
Amandine Aubert ◽  
Lionel Dantas de Morais ◽  
Stéphanie Pétremont ◽  
Nathalie Labat ◽  
Hélène Frémont
Keyword(s):  
Failure Analysis ◽  
Plasma Etching ◽  
Wet Etching ◽  
Preparation Process ◽  
Front Side ◽  
Plastic Packages ◽  
Dielectric Layers ◽  
Plastic Package ◽  
Low K ◽  
Organic Dielectric

Abstract This paper presents a new sample preparation process for front side access for die with organic dielectric layers that are encapsulated in plastic packages. The limitation of the standard failure analysis flow is firstly described, showing the damage caused by wet etching. Then, the decapsulation method combining laser ablation and plasma etching is presented. It is completed by the process optimization. The final process makes it possible to perform failure analysis on low-k/Cu technologies in plastic package either by the front side or by the backside of the die.

Precision Xe Plasma FIB Delayering for Physical Failure Analysis of Sub-20 nm Microprocessor Devices

2017 ◽  
Author(s):  
D. Zudhistira ◽  
V. Viswanathan ◽  
V. Narang ◽  
J.M. Chin ◽  
S. Sharang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Dielectric Films ◽  
Planar Surface ◽  
Chemical Methods ◽  
Root Cause ◽  
Essential Step ◽  
Dielectric Layers ◽  
Wet Chemical ◽  
20 Nm ◽  
Low K

Abstract Deprocessing is an essential step in the physical failure analysis of ICs. Typically, this is accomplished by techniques such as wet chemical methods, RIE, and mechanical manual polishing. Manual polishing suffers from highly non-uniform delayering particularly for sub 20nm technologies due to aggressive back-end-of-line scaling and porous ultra low-k dielectric films. Recently gas assisted Xe plasma FIB has demonstrated uniform delayering of the metal and dielectric layers, achieving a planar surface of heterogeneous materials. In this paper, the successful application of this technique to delayer sub-20 nm microprocessor chips with real defects to root cause the failure is presented.

Interconnect and Gate Level Delayering Techniques for Cu/Low k Technology Failure Analysis

2003 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Barry Dutt ◽  
Tony Bucha ◽  
Joe Serpiello
Keyword(s):  
Failure Analysis ◽  
Chemical Mechanical Polishing ◽  
Failure Modes ◽  
Reactive Ion Etching ◽  
Mechanical Polishing ◽  
Front Side ◽  
Ion Etching ◽  
Low K

Abstract In this paper, Failure Analysis (FA) challenges, reliability issues, and new failure modes for copper technology will be presented. Deprocessing techniques for copper technology have been developed and will be discussed. Front side and backside FA deprocessing techniques for copper layers and low k inter-level dielectric (ILD) layers including: reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and a combination of these techniques will be discussed. In addition, novel gate level deprocessing techniques will be presented.

Failure analysis case study on a Cu/low-k technology in package: New front-side approach using laser and plasma de-processing

2010 ◽  
Vol 50 (9-11) ◽  
pp. 1688-1691 ◽  
Author(s):  
A. Aubert ◽  
J.P. Rebrassé ◽  
L. Dantas de Morais ◽  
N. Labat ◽  
H. Frémont
Keyword(s):  
Failure Analysis ◽  
Front Side ◽  
Low K

Novel Failure Analysis Sample Preparation Techniques for PoP Packaging

2012 ◽  
Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanisms ◽  
Preparation Process ◽  
Space Saving ◽  
Optical Probing ◽  
Preparation Techniques

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.

A Review of Wet Etch Formulas for Silicon Semiconductor Failure Analysis

1996 ◽  
Author(s):  
T.W. Lee
Keyword(s):  
Failure Analysis ◽  
Literature Search ◽  
Wet Etching ◽  
Second Step ◽  
Environmental Concerns ◽  
Acid System ◽  
Graphical Data ◽  
Selective Etch ◽  
Chromium Compounds ◽  
Wet Etch

Abstract WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.

A Novel Junction Profiling Methodology

2010 ◽  
Author(s):  
Tomokazu Nakai
Keyword(s):  
Failure Analysis ◽  
Profile Analysis ◽  
Semiconductor Devices ◽  
Wet Etching ◽  
Two Dimensional ◽  
Electrical Characteristics ◽  
Conventional Methods

Abstract Currently many methods are available to obtain a junction profile of semiconductor devices, but the conventional methods have drawbacks, and they could be obstacles for junction profile analysis. This paper introduces an anodic wet etching-based two-dimensional junction profiling method, which is practical, efficient, and reliable for failure analysis and electrical characteristics evaluation.

Backside Mechanical Preparation Methodology for Effective Failure Analysis on Small and Non-Exposed Die Paddle Package

2018 ◽  
Author(s):  
Ong Pei Hoon ◽  
Ng Kiong Kay ◽  
Gwee Hoon Yen
Keyword(s):  
Failure Analysis ◽  
Chemical Etching ◽  
Chemical Resistance ◽  
Etching Time ◽  
Lead Frame ◽  
Front Side ◽  
Electrical Measurements ◽  
Mechanical Preparation ◽  
Die Surface ◽  
Copper Lead

Abstract Chemical etching is commonly used in exposing the die surface from die front-side and die backside because of its quick etching time, burr-free and stress-free. However, this technique is risky when performing copper lead frame etching during backside preparation on small and non-exposed die paddle package. The drawback of this technique is that the copper leads will be over etched by 65% Acid Nitric Fuming even though the device’s leads are protected by chemical resistance tape. Consequently, the device is not able to proceed to any other further electrical measurements. Therefore, we introduced mechanical preparation as an alternative solution to replace the existing procedure. With the new method, we are able to ensure the copper leads are intact for the electrical measurements to improve the effectiveness and accuracy of physical failure analysis.

Gallium Arsenide Integrated Circuits Decapsulation Technique Using Mixed Acid Chemistry For Die-Level Failure Analysis

2018 ◽  
Author(s):  
Harold Jeffrey M. Consigo ◽  
Ricardo S. Calanog ◽  
Melissa O. Caseria
Keyword(s):  
Gallium Arsenide ◽  
Sulfuric Acid ◽  
Nitric Acid ◽  
Integrated Circuits ◽  
Failure Analysis ◽  
Mixed Acid ◽  
Optimum Parameters ◽  
Plastic Package ◽  
Fuming Nitric Acid ◽  
Concentrated Sulfuric Acid

Abstract Gallium Arsenide (GaAs) integrated circuits have become popular these days with superior speed/power products that permit the development of systems that otherwise would have made it impossible or impractical to construct using silicon semiconductors. However, failure analysis remains to be very challenging as GaAs material is easily dissolved when it is reacted with fuming nitric acid used during standard decapsulation process. By utilizing enhanced chemical decapsulation technique with mixture of fuming nitric acid and concentrated sulfuric acid at a low temperature backed with statistical analysis, successful plastic package decapsulation happens to be reproducible mainly for die level failure analysis purposes. The paper aims to develop a chemical decapsulation process with optimum parameters needed to successfully decapsulate plastic molded GaAs integrated circuits for die level failure analysis.

Failure Modes, Reliability Analysis and Case Studies on the Integration of Copper and Low-K Technology

2004 ◽  
Author(s):  
Huixian Wu ◽  
James Cargo ◽  
Huixian Wu ◽  
Marvin White
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Copper Interconnects ◽  
Wet Chemical ◽  
Low K ◽  
Section Analysis

Abstract The integration of copper interconnects and low-K dielectrics will present novel failure modes and reliability issues to failure analysts. This paper discusses failure modes related to Cu/low-K technology. Here, physical failure analysis (FA) techniques including deprocessing and cross-section analysis have been developed. The deprocessing techniques include wet chemical etching, reactive ion etching, chemical mechanical polishing and a combination of these techniques. Case studies on different failure modes related to Cu/low k technology are discussed: copper voiding, copper extrusion; electromigration stress failure; dielectric cracks; delamination-interface adhesion; and FA on circuit-under-pad. For the cross-section analysis of copper/low-K samples, focused ion beam techniques have been developed. Scanning electron microscopy, EDX, and TEM analytical analysis have been used for failure analysis for Cu/low-K technology. Various failure modes and reliability issues have also been addressed.

Sign in / Sign up

Export Citation Format

Share Document