Failure Analysis of ILD Delamination—Uncovering Multiple Root Causes

2015 ◽  
Author(s):  
Marie Castignolles ◽  
Thomas Zirilli ◽  
Eric Cattey ◽  
Justin Lewenstein ◽  
Steve Schauer ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Optical Microscopy ◽  
Cross Sections ◽  
Multiple Root ◽  
Wafer Fabrication ◽  
Multiple Factors ◽  
Initial Failure ◽  
Underlying Causes ◽  
Complete Set

Abstract FA cannot consist of simply jumping to conclusions. The FA process is validated through correlation with the initial failure and through interpretation of the obtained results, subjective by definition. This paper illustrates the difficulty of analyzing complex failures caused by multiple factors, including wafer fabrication, assembly, and application conditions. Inter-Layer Dielectric (ILD) delamination was experienced on various ICs from the same 250nm technology. A complete set of techniques (C-SAM, laser and optical microscopy, SEM, FIB cross-sections, TEM, EFTEM, SIMS, Auger, delineation) was used as different pieces of the same puzzle to reveal the multiple factors contributing to the ILD delamination failures. Due to the subtle nature of some of the underlying causes, defining an accurate FA approach with appropriate sample preparation and accurate device traceability was critical to understanding this complex, multivariate issue.

Failure Analysis of Flip Chip C4 Package Using Focused Ion Beam Milling Technique

2011 ◽  
Author(s):  
Lihong Cao ◽  
Loc Tran ◽  
Wallace Donna
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Cross Sections ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Failure Mechanisms ◽  
Organic Substrate ◽  
Dual Beam ◽  
Preparation Techniques

Abstract This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. Dual- Beam Focused Ion Beam (DB FIB) cross sections were successful in detecting failure mechanisms related either to the die/C4 bump or package defect inside the organic substrate. This paper outlines detailed sample preparation techniques prior to performing the DB FIB cross-sections, along with case studies of DB FIB cross-sections.

A technique for preparing semiconductor cross sections for both TEM and SEM analysis

1989 ◽  
Vol 47 ◽  
pp. 712-713
Author(s):  
Stanley J. Klepeis ◽  
J.P. Benedict ◽  
R.M Anderson
Keyword(s):  
Sample Preparation ◽  
Cross Section ◽  
Cross Sections ◽  
Sem Analysis ◽  
Preparation Technique ◽  
Ion Milling ◽  
Tem Analysis ◽  
Polished Cross Section ◽  
Area Of Interest ◽  
Polished Side

The ability to prepare a cross-section of a specific semiconductor structure for both SEM and TEM analysis is vital in characterizing the smaller, more complex devices that are now being designed and manufactured. In the past, a unique sample was prepared for either SEM or TEM analysis of a structure. In choosing to do SEM, valuable and unique information was lost to TEM analysis. An alternative, the SEM examination of thinned TEM samples, was frequently made difficult by topographical artifacts introduced by mechanical polishing and lengthy ion-milling. Thus, the need to produce a TEM sample from a unique,cross-sectioned SEM sample has produced this sample preparation technique.The technique is divided into an SEM and a TEM sample preparation phase. The first four steps in the SEM phase: bulk reduction, cleaning, gluing and trimming produces a reinforced sample with the area of interest in the center of the sample. This sample is then mounted on a special SEM stud. The stud is inserted into an L-shaped holder and this holder is attached to the Klepeis polisher (see figs. 1 and 2). An SEM cross-section of the sample is then prepared by mechanically polishing the sample to the area of interest using the Klepeis polisher. The polished cross-section is cleaned and the SEM stud with the attached sample, is removed from the L-shaped holder. The stud is then inserted into the ion-miller and the sample is briefly milled (less than 2 minutes) on the polished side. The sample on the stud may then be carbon coated and placed in the SEM for analysis.

Comparison of ultra high resolution immersion lens CFESEM and TEM for imaging of semiconductor devices

1990 ◽  
Vol 48 (4) ◽  
pp. 622-623
Author(s):  
Terrence Reilly ◽  
Al Pelillo ◽  
Barbara Miner
Keyword(s):  
High Resolution ◽  
Sample Preparation ◽  
Cross Sections ◽  
Semiconductor Devices ◽  
Ion Milling ◽  
Observation Area ◽  
Transmission Electron ◽  
Milling Machines ◽  
Resolution Imaging ◽  
Electron Microscopes

The use of transmission electron microscopes (TEM) has proven to be very valuable in the observation of semiconductor devices. The need for high resolution imaging becomes more important as the devices become smaller and more complex. However, the sample preparation for TEM observation of semiconductor devices have generally proven to be complex and time consuming. The use of ion milling machines usually require a certain degree of expertise and allow a very limited viewing area. Recently, the use of an ultra high resolution "immersion lens" cold cathode field emission scanning electron microscope (CFESEM) has proven to be very useful in the observation of semiconductor devices. Particularly at low accelerating voltages where compositional contrast is increased. The Hitachi S-900 has provided comparable resolution to a 300kV TEM on semiconductor cross sections. Using the CFESEM to supplement work currently being done with high voltage TEMs provides many advantages: sample preparation time is greatly reduced and the observation area has also been increased to 7mm. The larger viewing area provides the operator a much greater area to search for a particular feature of interest. More samples can be imaged on the CFESEM, leaving the TEM for analyses requiring diffraction work and/or detecting the nature of the crystallinity.

Novel Failure Analysis Sample Preparation Techniques for PoP Packaging

2012 ◽  
Author(s):  
Ng Sea Chooi ◽  
Chor Theam Hock ◽  
Ma Choo Thye ◽  
Khoo Poh Tshin ◽  
Dan Bockelman
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Failure Mechanisms ◽  
Preparation Process ◽  
Space Saving ◽  
Optical Probing ◽  
Preparation Techniques

Abstract Trends in the packaging of semiconductors are towards miniaturization and high functionality. The package-on-package(PoP) with increasing demands is beneficial in cost and space saving. The main failure mechanisms associated with PoP technology, including open joints and warpage, have created a lot of challenges for Assembly and Failure Analysis (FA). This paper outlines the sample preparation process steps to overcome the challenges to enable successful failure analysis and optical probing.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Studies on a Failure Analysis Flow of Surface Contamination, Corrosion, and Underetch on Microchip Al Bondpads in Wafer Fabrication

2005 ◽  
Author(s):  
Hua Younan
Keyword(s):  
Failure Analysis ◽  
Galvanic Corrosion ◽  
Surface Contamination ◽  
Wafer Fabrication ◽  
Tof Sims ◽  
Corrosion Passivation

Abstract A failure analysis flow is developed for surface contamination, corrosion and underetch on microchip Al bondpads and it is applied in wafer fabrication. SEM, EDX, Auger, FTIR, XPS and TOF-SIMS are used to identify the root causes. The results from carbon related contamination, galvanic corrosion, fluorine-induced corrosion, passivation underetch and Auger bondpad monitoring will be presented. The failure analysis flow will definitely help us to select suitable methods and tools for failure analysis of Al bondpad-related issues, identify rapidly possible root causes of the failures and find the eliminating solutions at both wafer fabrication and assembly houses.

A New Deprocess Flow of Failure Analysis for MEMS Motion Sensor

2013 ◽  
Author(s):  
Chun-An Huang ◽  
Han-Yun Long ◽  
King-Ting Chiang ◽  
Li Chuang ◽  
Kevin Tsui
Keyword(s):  
Failure Analysis ◽  
Optical Microscopy ◽  
Motion Sensor ◽  
Thermal System ◽  
Layer By Layer ◽  
Sensor Failure ◽  
Process Flow ◽  
New Process ◽  
Cutting System ◽  
Successful Observation

Abstract This paper demonstrates a new de-process flow for MEMS motion sensor failure analysis, using layer by layer deprocessing to locate defect points. Analysis tools used in this new process flow include IR optical microscopy, thermal system, SEM and a cutting system to de-process of MEMS motion sensor and successful observation defect points.

Thin-Die Flip Chip Physical-FA Process Flow

2002 ◽  
Author(s):  
Andrew J. Komrowski ◽  
N. S. Somcio ◽  
Daniel J. D. Sullivan ◽  
Charles R. Silvis ◽  
Luis Curiel ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Organic Substrate ◽  
Fault Isolation ◽  
Preparation Methods ◽  
Chip Technology ◽  
Isolation Test ◽  
Sample Preparation Methods

Abstract The use of flip chip technology inside component packaging, so called flip chip in package (FCIP), is an increasingly common package type in the semiconductor industry because of high pin-counts, performance and reliability. Sample preparation methods and flows which enable physical failure analysis (PFA) of FCIP are thus in demand to characterize defects in die with these package types. As interconnect metallization schemes become more dense and complex, access to the backside silicon of a functional device also becomes important for fault isolation test purposes. To address these requirements, a detailed PFA flow is described which chronicles the sample preparation methods necessary to isolate a physical defect in the die of an organic-substrate FCIP.

Sign in / Sign up

Export Citation Format

Share Document