Light-Induced Capacitance Alteration for Nondestructive Fault Isolation in TSV Structures for 3D Integration

2016 ◽  
Author(s):  
K.J.P. Jacobs ◽  
A. Khaled ◽  
M. Stucchi ◽  
T. Wang ◽  
M. Gonzalez ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Fault Isolation ◽  
Signal Generation ◽  
Wafer Level ◽  
3D Integration ◽  
Scanning Optical Microscopy ◽  
Voltage Contrast ◽  
Non Destructive ◽  
Electrical Connectivity ◽  
Scanning Electron

Abstract We report on a new non-destructive electrical fault isolation (EFI) technique to localize interconnection failures in through-silicon via (TSV) structures for three-dimensional (3-D) integration. The scanning optical microscopy (SOM) technique is based on light-induced capacitance alteration (LICA) and uses localized photon probing of TSV interconnect capacitance to localize interruptions of electrical connectivity. The technique is applicable to passivated devices and allows rapid, efficient, and non-destructive fault isolation at wafer level. We describe the physics behind signal generation of the technique and demonstrate the TSV photocapacitance effect. We further demonstrate the LICA technique on open failed TSV daisy chain structures and confirm our results with microprobing and voltage contrast measurements in a scanning electron microscope (SEM).

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

In FAB 300mm Wafer Level Atomic Force Probe Characterization

2012 ◽  
Author(s):  
Terence Kane
Keyword(s):  
Electrical Characterization ◽  
Dark Field ◽  
Wafer Level ◽  
Electrical Measurements ◽  
Manufacturing Line ◽  
Atomic Force ◽  
Monitoring Tools ◽  
Voltage Contrast ◽  
The Cost ◽  
Non Destructive

Abstract A 300mm wafer atomic force prober (AFP) has been installed into IBM’s manufacturing line to enable rapid, nondestructive electrical identification of defects. Prior to this tool many of these defects could not detected until weeks or months later. Moving failure analysis to the FAB provides a means of complementing existing FAB inspection and defect review tools as well as providing independent, non-destructive electrical measurements at an early point in the manufacturing cycle [1] Once the wafer sites are non destructively AFP characterized, the wafer is returned to its front opening unified pod (FOUP) carrier and may be reintroduced into the manufacturing line without disruption for further inspection or processing. Whole wafer atomic force probe electrical characterization has been applied to 32nm, 28nm, 20nm and 14nm node technologies. In this paper we explore the cost benefits of performing non-destructive AFP measurements on whole wafers. We have found the methodology of employing a whole wafer AFP tool complements existing in-line manufacturing monitoring tools such as brightfield/dark field optical inspection, SEM in-line inspection and in-line E-beam voltage contrast inspection (EBI).

scholarly journals Wafer-Level 3D Integration Based on Poly (Diallyl Phthalate) Adhesive Bonding

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1586
Author(s):  
Zhong Fang ◽  
Peng You ◽  
Yijie Jia ◽  
Xuchao Pan ◽  
Yunlei Shi ◽  
...  
Keyword(s):  
Adhesive Bonding ◽  
Low Cost ◽  
Three Dimensional ◽  
System Level ◽  
Process Conditions ◽  
Wafer Level ◽  
3D Integration ◽  
Bonding Pressure ◽  
Curing Conditions ◽  
Integration Technology

Three-dimensional integration technology provides a promising total solution that can be used to achieve system-level integration with high function density and low cost. In this study, a wafer-level 3D integration technology using PDAP as an intermediate bonding polymer was applied effectively for integration with an SOI wafer and dummy a CMOS wafer. The influences of the procedure parameters on the adhesive bonding effects were determined by Si–Glass adhesive bonding tests. It was found that the bonding pressure, pre-curing conditions, spin coating conditions, and cleanliness have a significant influence on the bonding results. The optimal procedure parameters for PDAP adhesive bonding were obtained through analysis and comparison. The 3D integration tests were conducted according to these optimal parameters. In the tests, process optimization was focused on Si handle-layer etching, PDAP layer etching, and Au pillar electroplating. After that, the optimal process conditions for the 3D integration process were achieved. The 3D integration applications of the micro-bolometer array and the micro-bridge resistor array were presented. It was confirmed that 3D integration based on PDAP adhesive bonding is suitable for the fabrication of system-on-chip when using MEMS and IC integration and that it is especially useful for the fabrication of low-cost suspended-microstructure on-CMOS-chip systems.

Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration

2004 ◽  
Vol 816 ◽  
Author(s):  
J.-Q. Lu ◽  
G. Rajagopalan ◽  
M. Gupta ◽  
T.S. Cale ◽  
R.J. Gutmann
Keyword(s):  
Wafer Bonding ◽  
Three Dimensional ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
3D Integration ◽  
Edge Chipping ◽  
3D Ics ◽  
Process Compatibility ◽  
Wafer Thinning ◽  
Thinning Process

AbstractMonolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described.

Fault Isolation on High Resistance Failure of 45nm ET Via Chains Using Combined Technique of SEM PVC and Nanoprobing

2010 ◽  
Author(s):  
P.K. Tan ◽  
Z.H. Mai ◽  
Y.W. Goh ◽  
L. Zhu ◽  
S.L. Toh ◽  
...  
Keyword(s):  
Electron Microscope ◽  
High Resistance ◽  
Fault Isolation ◽  
Divide And Conquer ◽  
Electrical Performance ◽  
Process Line ◽  
Scaling Down ◽  
Voltage Contrast ◽  
Combined Technique ◽  
Scanning Electron

Abstract Electrical Test (ET) structures are used to monitor the health and yield of a process line. With the scaling down of semiconductor devices to nanometer ranges, the number of metal lines and vias increase. In order to simulate the electrical performance of devices and to increase the sensitivity for line health check, ET structures are designed to be more complicated with a larger area. Hence, fault isolation and failure analysis become more challenging. In this paper, the combined technique of Scanning Electron Microscope (SEM) Passive Voltage Contrast (PVC), Nanoprobing technique, and Divide and Conquer Method (DCM) are proposed to locate open failure and high resistance failure in an ET via chain.

Principles and Possibilities of Backscattered Electron Micro-Tomography in the Scanning Electron Microscope

1997 ◽  
Vol 3 (S2) ◽  
pp. 497-498
Author(s):  
E I Rau ◽  
VNE Robinson
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Ion Beam ◽  
Three Dimensional ◽  
Major Disadvantage ◽  
Layer Structures ◽  
Backscattered Electron ◽  
Micro Tomography ◽  
Non Destructive ◽  
Scanning Electron

Multi layer structures are widely used in micro electronics devices and visualisation of their sub surface layers is important to understand the nature and properties of these devices. One of the more common methods of sub surface imaging is ion beam milling, in which sections of the overlaying material are removed to reveal sub surface details. Some disadvantages of this technique are that the equipment required is expensive and the technique is destructive. Another technique is to image a device at different accelerating voltages and determine at which voltage a particular feature is first detected. A major disadvantage of this technique is that the underlying layers are always observed partially obscured by the overlaying material. The development of a non destructive technique for three dimensional characterisation of electronic, physical, compositional and/or topological properties of these structures could be useful.One such technique is micro tomography using the backscattered electron (BSE) signal in the scanning electron microscope SEM [1].

Fault Identification by Use of a Simulated Passive Voltage Contrast Reference CAD Display

2006 ◽  
Author(s):  
R. Fredrickson
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Semiconductor Device ◽  
Fault Isolation ◽  
Fault Identification ◽  
Circuit Element ◽  
Design Rules ◽  
Voltage Contrast ◽  
Scanning Electron ◽  
Open Connection

Abstract Passive voltage contrast (PVC) is a phenomenon seen while inspecting a semiconductor device where imaged circuit features have a different value of contrast depending on whether that feature has an electrical path to ground, another circuit element, or has an open connection. A common method of fault isolation during failure analysis is to use these contrast values to determine if a feature is incorrectly connected indicating a defect is present. This paper discusses a fault identification method by creating a simulated PVC reference that can be displayed next to the scanning electron microscope PVC image for a comparison of the expected PVC. The procedure of how to create the PVC reference is discussed using functions found in tools typically used to run a Design Rules Check in commonly available software. Three examples are given of how this methodology could be used to provide further analysis capabilities during fault isolation.

Application of Electro Optical Terahertz Pulse Reflectometry for Fault Localization and Defect Analysis

2017 ◽  
Author(s):  
Yi-Sheng Lin ◽  
Yu-Hsiang Hsiao ◽  
Shu-Hua Lee
Keyword(s):  
Failure Analysis ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Defect Analysis ◽  
Wafer Level ◽  
Terahertz Pulse ◽  
Electrical Failure ◽  
Analysis Technique ◽  
Destructive Analysis ◽  
Non Destructive

Abstract Electro Optical Terahertz Pulse Reflectometry (EOTPR) is an E-FA (Electrical Failure Analysis) technique in the semiconductor industry for non-destructive electrical fault isolation for shorts, leakages and opens. This paper introduces the capability and presents several case studies identifying the physical location of defects where EOTPR is useful as a non-destructive analysis technique. In this paper, the methodology and application of EOTPR on open and short failure isolations in advanced 2.5D IC and wafer level packages (WLP) have been presented. The experimental results of P-FA (Physical Failure Analysis) verify the accuracy of the EOTPR system in determining the distance to defect.

Low-Temperature PETEOS-to-PETEOS Wafer Bonding Using Titanium as Bonding Intermediate

2006 ◽  
Vol 914 ◽  
Author(s):  
Jian Yu ◽  
Richard L. Moore ◽  
Sang Hwui Lee ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Low Temperature ◽  
Wafer Bonding ◽  
Electron Spectroscopy ◽  
Auger Electron ◽  
Three Dimensional ◽  
3D Integration ◽  
Patterned Wafers ◽  
Scanning Electron

AbstractBonding of pre-processed silicon wafers at back-end-of-the-line (BEOL) compatible conditions is one of the attractive approaches for three-dimensional (3D) integration. Among various technologies being evaluated, bonding of low temperature oxides (e.g., plasma-enhanced tetraethylorthosilicate (PETEOS)) is of great interest. In this work, we report low-temperature PETEOS-to-PETEOS wafer bonding, using a thin layer of titanium (Ti) as bonding intermediate. The bonding strength is evaluated qualitatively, while the bonding interface is examined by Auger electron spectroscopy (AES) and scanning electron microscopy (SEM). Preliminary results of PETEOS/Ti/PETEOS bonding on patterned wafers with single-level Cu damascene structures are also discussed.

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