A Case Study of Trapped Charge Induced Surface Leakage

2017 ◽  
Author(s):  
Xiang-Dong Wang ◽  
Xu Cheng ◽  
Evgueniy Stefanov ◽  
William Godek
Keyword(s):  
Silicon Crystal ◽  
Electrical Characterization ◽  
Diagnostic Techniques ◽  
Large Area ◽  
Dopant Profiling ◽  
Atomic Force ◽  
Localized Defects ◽  
Dielectric Charge ◽  
Surface Leakage

Abstract In many cases, the leakage is relatively small and tends to spread out over a relatively large area. While diagnostic techniques using laser stimulation, such as OBIRCH, or photoemission are powerful in identifying localized defects in silicon crystal and backend metal layers, they are found to be not as sensitive in isolating charge induced leakage. This paper presents a case study of dielectric charge induced leakage in a high voltage ESD device. In this case, conventional photoemission and laser probing diagnostic techniques were not able to localize leakage sites. By using atomic force probing for detailed electrical characterization of individual devices, experimenting with UV radiation, and SCM 2D dopant profiling analysis, it showed that trapped charges in dielectric layers cause leakage near silicon surface. Based on the finding, the FAB fixed the issue by implementing UV bake in the process.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Morphology and development of flow-pattern defect with extended nonagitated Secco etching

1994 ◽  
Vol 52 ◽  
pp. 868-869
Author(s):  
Y. Pan
Keyword(s):  
Flow Pattern ◽  
Silicon Crystal ◽  
Gate Oxide ◽  
Crystal Growth Rate ◽  
Etch Depth ◽  
Force Microscopy ◽  
Etch Pit ◽  
Float Zone ◽  
Atomic Force ◽  
Multiple Step

The D defect, which causes the degradation of gate oxide integrities (GOI), can be revealed by Secco etching as flow pattern defect (FPD) in both float zone (FZ) and Czochralski (Cz) silicon crystal or as crystal originated particles (COP) by a multiple-step SC-1 cleaning process. By decreasing the crystal growth rate or high temperature annealing, the FPD density can be reduced, while the D defectsize increased. During the etching, the FPD surface density and etch pit size (FPD #1) increased withthe etch depth, while the wedge shaped contours do not change their positions and curvatures (FIG.l).In this paper, with atomic force microscopy (AFM), a simple model for FPD morphology by non-crystallographic preferential etching, such as Secco etching, was established.One sample wafer (FPD #2) was Secco etched with surface removed by 4 μm (FIG.2). The cross section view shows the FPD has a circular saucer pit and the wedge contours are actually the side surfaces of a terrace structure with very small slopes. Note that the scale in z direction is purposely enhanced in the AFM images. The pit dimensions are listed in TABLE 1.

Impairment Tutorial: Neurological Impairment Evaluation: Overview of Sixth Edition Approaches

2008 ◽  
Vol 13 (2) ◽  
pp. 6-8
Author(s):  
Lorne Direnfeld ◽  
Christopher R. Brigham ◽  
Elizabeth Genovese
Keyword(s):  
Spinal Cord ◽  
Neurological Impairment ◽  
Diagnostic Techniques ◽  
Neurological Deficits ◽  
Sixth Edition ◽  
Pain Disability ◽  
Whole Person ◽  
Disability Questionnaire ◽  
Cervical Plating

Abstract The AMA Guides to the Evaluation of Permanent Impairment (AMA Guides), does not provide a Diagnosis-based estimate of impairment due to syringomyelia, a disorder in which a cyst (syrinx), develops within the central spinal cord and destroys neural tissue as it expands. The AMA Guides, however, does provide an approach to rating a syringomyelia based on objective findings of neurological deficits identified during a neurological examination and demonstrated by standard diagnostic techniques. Syringomelia may occur after spinal cord trauma, including a contusion of the cord. A case study illustrates the rating process: The case patient is a 46-year-old male who fell backwards, landing on his upper back and head; over a five-year period he received a T5-6 laminectomy and later partial corpectomies of C5, C6, and C7, cervical discectomy C5-6 and C6-7; iliac crest strut graft fusion of C5-6 and C6-7; and anterior cervical plating of C5 to C7 for treatment of myelopathy; postoperatively, the patient developed dysphagia. The evaluating physician should determine which conditions are ratable, rate each of these components, and combine the resulting whole person impairments without omission or duplication of a ratable impairment. The article includes a pain disability questionnaire that can be used in conjunction with evaluations conducted according to Chapter 3, Pain, and Chapter 17, The Spine.

Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy

2003 ◽  
Author(s):  
Jon C. Lee ◽  
J. H. Chuang
Keyword(s):  
Atomic Force Microscopy ◽  
Integrated Circuits ◽  
Fault Localization ◽  
Electrical Characterization ◽  
Conductive Atomic Force Microscopy ◽  
Force Microscopy ◽  
Atomic Force ◽  
Optical Electron ◽  
Defect Isolation ◽  
Voltage Contrast

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.

Case Studies in Atomic Force Probe Analysis

2006 ◽  
Author(s):  
Randal Mulder ◽  
Sam Subramanian ◽  
Tony Chrastecky
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Light Emission ◽  
Electrical Characterization ◽  
Logic Circuits ◽  
Contrast Imaging ◽  
Atomic Force ◽  
Measuring Surface ◽  
Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Die-Level Scanning Capacitance Microscopy Fault Isolation on SOI Fin-FET Devices for Advanced Semiconductor Nodes

2018 ◽  
Author(s):  
Lucile C. Teague Sheridan ◽  
Tanya Schaeffer ◽  
Yuting Wei ◽  
Satish Kodali ◽  
Chong Khiam Oh
Keyword(s):  
Atomic Force Microscopy ◽  
Failure Analysis ◽  
Fault Isolation ◽  
Scanning Capacitance Microscopy ◽  
Force Microscopy ◽  
Atomic Force

Abstract It is widely acknowledged that Atomic force microscopy (AFM) methods such as conductive probe AFM (CAFM) and Scanning Capacitance Microscopy (SCM) are valuable tools for semiconductor failure analysis. One of the main advantages of these techniques is the ability to provide localized, die-level fault isolation over an area of several microns much faster than conventional nanoprobing methods. SCM, has advantages over CAFM in that it is not limited to bulk technologies and can be utilized for fault isolation on SOI-based technologies. Herein, we present a case-study of SCM die-level fault isolation on SOI-based FinFET technology at the 14nm node.

Application of AFP in Resolving Systematic Issue in Wafer Fabrication

2013 ◽  
Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Mechanisms ◽  
Critical Role ◽  
Electrical Characterization ◽  
Process Technology ◽  
Atomic Force ◽  
Defect Localization ◽  
Non Volatile Memory ◽  
Visual Failure

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]

In FAB 300mm Wafer Level Atomic Force Probe Characterization

2012 ◽  
Author(s):  
Terence Kane
Keyword(s):  
Electrical Characterization ◽  
Dark Field ◽  
Wafer Level ◽  
Electrical Measurements ◽  
Manufacturing Line ◽  
Atomic Force ◽  
Monitoring Tools ◽  
Voltage Contrast ◽  
The Cost ◽  
Non Destructive

Abstract A 300mm wafer atomic force prober (AFP) has been installed into IBM’s manufacturing line to enable rapid, nondestructive electrical identification of defects. Prior to this tool many of these defects could not detected until weeks or months later. Moving failure analysis to the FAB provides a means of complementing existing FAB inspection and defect review tools as well as providing independent, non-destructive electrical measurements at an early point in the manufacturing cycle [1] Once the wafer sites are non destructively AFP characterized, the wafer is returned to its front opening unified pod (FOUP) carrier and may be reintroduced into the manufacturing line without disruption for further inspection or processing. Whole wafer atomic force probe electrical characterization has been applied to 32nm, 28nm, 20nm and 14nm node technologies. In this paper we explore the cost benefits of performing non-destructive AFP measurements on whole wafers. We have found the methodology of employing a whole wafer AFP tool complements existing in-line manufacturing monitoring tools such as brightfield/dark field optical inspection, SEM in-line inspection and in-line E-beam voltage contrast inspection (EBI).

DIRECT GROWTH OF EPITAXIAL La0.67Ca0.33MnO3 - δ THIN FILMS

2002 ◽  
Vol 09 (05n06) ◽  
pp. 1611-1615 ◽  
Author(s):  
G. CAMPILLO ◽  
L. F. CASTRO ◽  
P. VIVAS ◽  
E. BACA ◽  
P. PRIETO ◽  
...  
Keyword(s):  
Thin Films ◽  
Substrate Surface ◽  
Electrical Characterization ◽  
Annealing Treatment ◽  
Pure Oxygen ◽  
X Ray Diffraction ◽  
Atomic Force ◽  
Transmission Electron ◽  
Afm Analysis ◽  
Direct Growth

La 0.67 Ca 0.33 MnO 3 - δ thin films were deposited using a high-pressure dc-sputtering process. Pure oxygen at a pressure of 3.8 mbar was used as sputtering gas. The films were grown on (001) LaAlO 3 and (001) SrTiO 3 substrates at heater temperature of 850° without any annealing treatment. The formation of highly a-axis-oriented films with sharp interface with substrate surface is demonstrated by X-ray diffraction, transmission electron microscope (TEM), and atomic force microscope (AFM) analysis. Electrical characterization revealed a metal–insulator transition at T MI = 276 K, and magnetic characterization showed good magnetic properties with a PM–FM transition at TC ≈ 262 K.

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