Laser Chemical Etching Trench Refinements for Backside Debug Journey to the Circuit Layer

Author(s):  
Matthew M. Mulholland ◽  
Shida Tan ◽  
Muhammad Usman Raza ◽  
Matthew Levesque ◽  
Jordan Furlong ◽  
...  

Abstract The journey to the circuit layer will be described by first discussing baseline processes of laser assisted chemical etching (LACE) steps before the focused ion beam (FIB) workflow. These LACE processes take advantage of a dual 532 nm continuous wave (CW) and pulse laser system, however limitations and overhead that is transferred over to the FIB operator will be demonstrated. Experiments show an additional third 355 nm ultraviolet (UV) pulse laser process introduction into the workflow can further reduce the remaining silicon thickness (RST) relieving FIB overhead. In addition, complex pulse laser patterning techniques will show a refinement to nonuniform produced silicon. Finally, other pulse laser patterning techniques such as polygon etch capability will allow laser etching around and in-between features to enhance circuit layer accessibility for debug operations.

Author(s):  
Matthew M. Mulholland ◽  
Scott Silverman

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require backside sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces will typically use conventional Laser Chemical Etching (LCE) platforms. The focus of this analysis will be to investigate and conjoin previously published techniques to this local preparation by using a combination of laser sources. A Continuous Wave (CW) and Pulse laser will be used at various processing stages to de-process IC packaging materials silicon and mold compound encapsulation.


Author(s):  
Jim B. Colvin

Abstract A new method of preparation will be shown which allows traditional fixturing such as test heads and probe stations to be utilized in a normal test mode. No inverted boards cabled to a tester are needed since the die remains in its original package and is polished and rebonded to a new package carrier with the polished side facing upward. A simple pin reassignment is all that is needed to correct the reverse wire sequence after wire to wire bonding or wire to frame bonding in the new package frame. The resulting orientation eliminates many of the problems of backside microscopy since the resulting package orientation is now frontside. The low profile as a result of this technique allows short working distance objectives such as immersion lenses to be used across the die surface. Test equipment can be used in conjunction with analytical tools such as the emission microscope or focused ion beam due to the upright orientation of the polished backside silicon. The relationship between silicon thickness and transmission for various wavelengths of light will be shown. This preparation technique is applicable to advanced packaging methods and has the potential to become part of future assembly processes.


Metals ◽  
2019 ◽  
Vol 9 (12) ◽  
pp. 1346
Author(s):  
Yannick Champion ◽  
Mathilde Laurent-Brocq ◽  
Pierre Lhuissier ◽  
Frédéric Charlot ◽  
Alberto Moreira Jorge Junior ◽  
...  

A silver-based nanoporous material was produced by dealloying (selective chemical etching) of an Ag38.75Cu38.75Si22.5 crystalline alloy. Composed of connected ligaments, this material was imaged using a scanning electron microscope (SEM) and focused ion-beam (FIB) scanning electron microscope tomography. Its mechanical behavior was evaluated using nanoindentation and found to be heterogeneous, with density variation over a length scale of a few tens of nanometers, similar to the indent size. This technique proved relevant to the investigation of a material’s mechanical strength, as well as to how its behavior related to the material’s microstructure. The hardness is recorded as a function of the indent depth and a phenomenological description based on strain gradient and densification kinetic was proposed to describe the resultant depth dependence.


1992 ◽  
Vol 279 ◽  
Author(s):  
Wei Chen ◽  
P. Chen ◽  
A. Madhukar ◽  
R. Viswanathan ◽  
J. So

ABSTRACTWe report the realization of free standing 3D structures as tall as ∼ 7μm with nano-scale thickness in Si using the technique of Ga focused ion beam implantation and sputtering followed by wet chemical etching. Some of the previously investigated subjects such as anisotropie etching behavior of crystalline Si and etch stop effect of Ga+implanted Si etched in certain anisotropie chemical etchants have been further explored with the emphasis on exploiting them in realizing free standing structures. The design and fabrication considerations in achieving such free standing structures are discussed and some typical structures fabricated by this technique are shown.


Author(s):  
Scott Silverman ◽  
Richard Aucoin ◽  
Daniel Ehrlich ◽  
Kenneth Nill

Abstract Laser microchemical etching systems provide enhanced through-wafer IR viewing and provide access for focused ion beam (FIB) tools and e-beam testers on flip-chip packaged die [1]. In demanding applications, laser etching is directed at rates of 100,000 cubic micrometers per second and must be stopped within 10 to 15 micrometers (thickness remaining) of the active flip-chip circuit. In cases where the initial die thickness is known, the laser process is sufficiently reproducible and system depth of focus is sufficiently narrow to place the laseretched floor within an accuracy of about plus or minus 5 micrometers relative to the initial surface of the die. However, greater accuracy is often desired to minimize FIB etch time. In addition, the laser step is often proceeded by a mechanical thinning operation on the die. This mechanical process introduces an uncertainty in initial part thickness, as well as part wedge and bowing. In this paper we describe an optical beam induced current (OBIC) method for accurate closed-loop endpointing with direct reference to the active device surface on the flipped die. The method relies on an exponentially increasing current that is induced by the laser as the device is thinned. Because of the strong absorption of the silicon bulk at visible wavelengths, the signal is sensitive to submicrometer thickness changes and, hence, may be used to stop the laser etching process with high accuracy at the desired 10 to 15 micrometer distance from the active circuit. The new technique has been studied on commercially available devices and shown to be insensitive to localized device junction density. Hence, endpointing is not highly dependent on the circuit design or exact placement of circuit elements. We outline the substrate and circuit properties that are most relevant to accurate implementation of the technique. The laser-etch process dependency of the OBIC signal has also been characterized. Simple high-speed closed loop electronics have been developed in order to apply the method for in situ endpointing New failure analysis/circuit debug techniques, including spectroscopic photoemission and picosecond time-resolved methods rely on observation of weak optical signals through the wafer. These would optimally be viewed though a remaining silicon thickness of a few micrometers or less. The limits of the OBIC endpointing method have been explored for the high-speed preparation of ultra thin local viewing windows in support of these new techniques.


2004 ◽  
Vol 2004.5 (0) ◽  
pp. 111-112
Author(s):  
Noritaka KAWASEGI ◽  
Noboru MORITA ◽  
Noboru TAKANO ◽  
Kiwamu ASHIDA ◽  
Jun TANIGUCHI ◽  
...  

1999 ◽  
Vol 38 (Part 1, No. 10) ◽  
pp. 6142-6144 ◽  
Author(s):  
Harald König ◽  
Johann Peter Reithmaier ◽  
Alfred Forchel

2008 ◽  
Vol 6 ◽  
pp. 265-272 ◽  
Author(s):  
C. Boit ◽  
R. Schlangen ◽  
A. Glowacki ◽  
U. Kindereit ◽  
T. Kiyan ◽  
...  

Abstract. Physical analysis for IC functionality in submicron technologies requires access through chip backside. Based upon typical global backside preparation with 50–100 µm moderate silicon thickness remaining, a state of the art of the analysis techniques available for this purpose is presented and evaluated for functional analysis and layout pattern resolution potential. A circuit edit technique valid for nano technology ICs, is also presented that is based upon the formation of local trenches using the bottom of Shallow Trench Isolation (STI) as endpoint for Focused Ion Beam (FIB) milling. As a derivative from this process, a locally ultra thin silicon device can be processed, creating a back surface as work bench for breakthrough applications of nanoscale analysis techniques to a fully functional circuit through chip backside. Several applications demonstrate the power and potential of this new approach.


Author(s):  
Matthew M. Mulholland ◽  
Ahmed A. Helmy ◽  
Anthony V. Dao

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.


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