OBIC Endpointing Method for Laser Thinning of Flip-Chip Circuits

Author(s):  
Scott Silverman ◽  
Richard Aucoin ◽  
Daniel Ehrlich ◽  
Kenneth Nill

Abstract Laser microchemical etching systems provide enhanced through-wafer IR viewing and provide access for focused ion beam (FIB) tools and e-beam testers on flip-chip packaged die [1]. In demanding applications, laser etching is directed at rates of 100,000 cubic micrometers per second and must be stopped within 10 to 15 micrometers (thickness remaining) of the active flip-chip circuit. In cases where the initial die thickness is known, the laser process is sufficiently reproducible and system depth of focus is sufficiently narrow to place the laseretched floor within an accuracy of about plus or minus 5 micrometers relative to the initial surface of the die. However, greater accuracy is often desired to minimize FIB etch time. In addition, the laser step is often proceeded by a mechanical thinning operation on the die. This mechanical process introduces an uncertainty in initial part thickness, as well as part wedge and bowing. In this paper we describe an optical beam induced current (OBIC) method for accurate closed-loop endpointing with direct reference to the active device surface on the flipped die. The method relies on an exponentially increasing current that is induced by the laser as the device is thinned. Because of the strong absorption of the silicon bulk at visible wavelengths, the signal is sensitive to submicrometer thickness changes and, hence, may be used to stop the laser etching process with high accuracy at the desired 10 to 15 micrometer distance from the active circuit. The new technique has been studied on commercially available devices and shown to be insensitive to localized device junction density. Hence, endpointing is not highly dependent on the circuit design or exact placement of circuit elements. We outline the substrate and circuit properties that are most relevant to accurate implementation of the technique. The laser-etch process dependency of the OBIC signal has also been characterized. Simple high-speed closed loop electronics have been developed in order to apply the method for in situ endpointing New failure analysis/circuit debug techniques, including spectroscopic photoemission and picosecond time-resolved methods rely on observation of weak optical signals through the wafer. These would optimally be viewed though a remaining silicon thickness of a few micrometers or less. The limits of the OBIC endpointing method have been explored for the high-speed preparation of ultra thin local viewing windows in support of these new techniques.

Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Scott L. Jansen ◽  
Andrew S. Dalton

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.


2003 ◽  
Vol 82 (8) ◽  
pp. 1281-1283 ◽  
Author(s):  
N. W. Liu ◽  
A. Datta ◽  
C. Y. Liu ◽  
Y. L. Wang

2012 ◽  
Vol 36 (3) ◽  
pp. 408-413 ◽  
Author(s):  
Sanket N. Bhavsar ◽  
Sivanandam Aravindan ◽  
P. Venkateswara Rao

2021 ◽  
Vol 10 (1) ◽  
pp. 2
Author(s):  
Elia Scattolo ◽  
Alessandro Cian ◽  
Damiano Giubertoni ◽  
Giovanni Paternoster ◽  
Luisa Petti ◽  
...  

The possibility of integrating plasmonic nanostructures directly on an active device, such as a silicon photodetector, is a challenging task of interest in many applications. Among the available nanofabrication techniques to realize plasmonic nanostructures, Focused Ion Beam (FIB) is surely the most promising, even if it is characterized by certain limitations, such as ion implantation in the substrate. In this work, we demonstrate the direct integration of plasmonic nanostructures directly on an active Si-photodetector by patterning a silver film with FIB. To avoid ion implantation and to therefore guarantee unaltered device behavior, both the patterning parameters and the geometry of the nanostructures were implemented by Montecarlo and Finite-Difference Time-Domain simulations.


Author(s):  
Yuanjing (Jane) Li ◽  
Steven Scott ◽  
Howard Lee Marks

Abstract This paper presents a backside chip-level physical analysis methodology using backside de-processing techniques in combination with optimized Scanning Electron Microscopic (SEM) imaging technique and Focused Ion Beam (FIB) cross sectioning to locate and analyze defects and faults in failing IC devices. The case studies illustrate the applications of the method for 28nm flip chip bulk Si CMOS devices and demonstrate how it is used in providing insight into the fab process and design for process and yield improvements. The methods are expected to play an even more important role during 20-nm process development and yield-ramping.


Author(s):  
Jane Y. Li ◽  
Chuan Zhang ◽  
John Aguada ◽  
Christopher Nemirow ◽  
Howard Marks

Abstract This paper demonstrates a methodology for chip level defect localization that allows complex logic nets to be approached from multiple perspectives during failure analysis of modern flip-chip CMOS IC devices. By combining chip backside deprocessing with site-specific plasma Focused Ion Beam (pFIB) low angle milling, the area of interest in a failure IC device is made accessible from any direction for nanoprobing and Electron Beam Absorbed Current (EBAC) analysis. This methodology allows subtle defects to be more accurately localized and analyzed for thorough root-cause understanding.


Author(s):  
Michael DiBattista ◽  
Corey Senowitz ◽  
Hasan Faraby ◽  
Prabhakar Bandaru

Abstract A key capability of focused ion beam (FIB) tools is the ability to deposit conductive materials by introducing organometallic precursors such as tungsten hexacarbonyl [W(CO)6] or (methylcyclopentadienl) trimethyl platinum [C9H17Pt]. The FIB deposited metal is often used in applications such as the modification of integrated circuits (ICs) by creating new electrical connection on the device. The electrical properties of the FIB material are of particular concern to high speed digital and radio frequency (RF) circuit designers because the resistivity of the FIB deposited metal is orders of magnitude higher in value than the near bulk resistivity value of the metals used in IC manufacturing. In this paper, we developed a correlation between the chemical composition of the FIB deposited metal and the electrical resistivity using an effective media theory (EMT) model. Analysis shows that gallium from the ion beam is the dominant contributor to lowering the resistivity of the jumper. The results of this work and model allow us to understand the role the chemical elements play in the electrical resistance of the FIB electrical jumper and to estimate the FIB metal resistance from energy dispersive spectroscopy (EDS) analysis and the geometry.


Author(s):  
Tejpal K. Hooghan ◽  
Kultaransingh Hooghan ◽  
Sho Nakahara ◽  
Robert K. Wolf ◽  
Robert W. Privette ◽  
...  

Abstract This paper describes a new diagnostic technique for analyzing microstructural changes occurring to flip chip joints after accelerated thermal tests. Flip chip reliability was assessed at high temperatures, with and without the application of electrical bias. A combination of standard metallurgical polishing techniques and the use of a focused ion beam (FIB) lift out technique was employed to make site-specific samples for transmission electron microscopy (TEM) cross-sections. We studied evaporated 95Pb/5Sn bumps, on sputtered Cr/CrCu/Cu/Au as the under bump metallization (UBM). Thermally stressed samples were tested for electrical continuity and evaluated using 50 MHz C-mode scanning acoustic microscopy (C-SAM). Failed samples were crosssectioned and large voids at the UBM were observed optically. TEM specimens taken from the predefined UBM region of degraded flip chip devices provided critical microstructural information, which led to a better understanding of a cause of degradation occurring in the flip chip joints.


Author(s):  
Raymond Lee ◽  
Nicholas Antoniou

Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of tradhional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its eflkcton device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology oflkrs access to diagnosing fdures in flip-chip assembled parts.


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