Supply voltage quality in low voltage industrial networks of Estonia

2011 ◽  
Vol 18 (2) ◽  
pp. 102 ◽  
Author(s):  
T Vinnal ◽  
K Janson ◽  
J Järvik ◽  
H Kalda ◽  
T Sakkos
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Industrial Networks ◽  
Voltage Quality

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1156
Author(s):  
Lorenzo Benvenuti ◽  
Alessandro Catania ◽  
Giuseppe Manfredini ◽  
Andrea Ria ◽  
Massimo Piotto ◽  
...  
Keyword(s):  
Low Voltage ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Clock Frequency ◽  
Design Environment ◽  
Ultra Low Power ◽  
Analog Cmos ◽  
Gain Error ◽  
Dc Gain

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

scholarly journals Low-voltage, low-power and high gain cmosota using active positive feedback with feed forward and FDCM techniques

2002 ◽  
Vol 15 (1) ◽  
pp. 93-101
Author(s):  
Lyes Bouzerara ◽  
Tahar Belaroussi ◽  
Boualem Amirouche
Keyword(s):  
Positive Feedback ◽  
Low Voltage ◽  
Supply Voltage ◽  
Phase Margin ◽  
Current Mirror ◽  
Power Supply Voltage ◽  
Gain Bandwidth ◽  
Frequency Dependent ◽  
Feed Forward ◽  
Current Mirrors

A low voltage, high dc gain and wideband load compensated cas code operational transconductance amplifier (OTA), using an active positive feedback with feed forward technique and frequency-dependent current mirrors (FDCM), is presented and analyzed. Such techniques stand as a powerful method of gain bandwidth and phase margin enhancements. In this paper, a frequency-dependent current mirror, whose input impedance increases with frequency, is used to form the feed forward path at the input of the current mirror with a feed forward capacitor. By using these techniques, the gain bandwidth product of the amplifier is improved from 115 MHz to 194 MHz, the phase margin is also improved from 85? to 95? and the gain is enhanced from 11 dB to 93 dB. This amplifier operates at 2.5 V power supply voltage drives a capacitive load of 1pF and gives a power dissipation of 7 mW. The predicted performance is verified by simulations using HSPICE tool with 0.8 fim CMOS AMS parameters.

scholarly journals Dynamic load modeling of some low voltage devices

2009 ◽  
Vol 22 (1) ◽  
pp. 61-70 ◽  
Author(s):  
Lidija Korunovic ◽  
Dobrivoje Stojanovic
Keyword(s):  
Induction Motor ◽  
Dynamic Load ◽  
Low Voltage ◽  
Supply Voltage ◽  
Incandescent Lamp ◽  
Mercury Lamp ◽  
Load Modeling ◽  
Load Model ◽  
Fluorescent Lamps

This paper presents the results of dynamic load modeling for some frequently used low voltage devices. The modeling of long-term dynamics is performed on the basis of step changes of supply voltage of the heater, incandescent lamp, mercury lamp, fluorescent lamps, refrigerator, TV set and induction motor. Parameters of dynamic exponential load model of these load devices are identified, analyzed and mutually compared.

scholarly journals Ladder-Based Synthesis and Design of Low-Frequency Buffer-Based CMOS Filters

Electronics ◽  
2021 ◽  
Vol 10 (23) ◽  
pp. 2931
Author(s):  
Waldemar Jendernalik ◽  
Jacek Jakusz ◽  
Grzegorz Blakiewicz
Keyword(s):  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Biomedical Sensors ◽  
Filter Synthesis ◽  
Cascade Method

Buffer-based CMOS filters are maximally simplified circuits containing as few transistors as possible. Their applications, among others, include nano to micro watt biomedical sensors that process physiological signals of frequencies from 0.01 Hz to about 3 kHz. The order of a buffer-based filter is not greater than two. Hence, to obtain higher-order filters, a cascade of second-order filters is constructed. In this paper, a more general method for buffer-based filter synthesis is developed and presented. The method uses RLC ladder prototypes to obtain filters of arbitrary orders. In addition, a set of novel circuit solutions with ultra-low voltage and power are proposed. The introduced circuits were synthesized and simulated using 180-nm CMOS technology of X-FAB. One of the designed circuits is a fourth-order, low-pass filter that features: 100-Hz passband, 0.4-V supply voltage, power consumption of less than 5 nW, and dynamic range above 60 dB. Moreover, the total capacitance of the proposed filter (31 pF) is 25% lower compared to the structure synthesized using a conventional cascade method (40 pF).

A CMOS Automatic Gain Control Circuit for Biomedical Applications

2015 ◽  
Vol 645-646 ◽  
pp. 1308-1313
Author(s):  
Zhi Qiang Gao ◽  
Fu Xiang Huang ◽  
Jing Li ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Exponential Function ◽  
Biomedical Applications ◽  
Low Voltage ◽  
Supply Voltage ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Cmos Technology ◽  
Chip Area ◽  
Gain Variation ◽  
Linearity Error

In this paper, a low-voltage automatic gain control (AGC) circuits is presented. The proposed circuit uses a novel approximated exponential function to increase the dB-linear output range. The three-stage AGC is fabricated in 0.18μm CMOS technology and shows the maximum gain variation of more than 100dB and a 67dB linear range with linearity error of less than ±1dB. The range of gain variation can be controlled from 34 to 101dB. The AGC dissipates less than 2.3mA under 1.8V supply voltage while occupying 0.4mm2 of chip area.

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