scholarly journals S Band Hybrid Power Amplifier in GaN Technology with Input/Output Multi Harmonic Tuned Terminations

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2318
Author(s):  
Sandro Ghisotti ◽  
Stefano Pisa ◽  
Paolo Colantonio
Keyword(s):  
Power Amplifier ◽  
Power Gain ◽  
Large Signal ◽  
Active Device ◽  
Hybrid Form ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Hybrid Power ◽  
Input And Output ◽  
Operating Bandwidth

In this paper, the design, fabrication, and measurements of an S band multi harmonic tuned power amplifier in GaN technology is described. The amplifier has been designed by exploiting second and third harmonic tuning conditions at both input and output ports of the active device. The amplifier has been realized in a hybrid form, and characterized in terms of small and large signal performance. An operating bandwidth of 300 MHz around 3.55 GHz, with 42.3 dBm output power, 9.3 dB power gain and 53.5% power added efficiency PAE (60% drain efficiency) at 3.7 GHz are measured.

Design of high-efficiency Hybrid Power Amplifier with concurrent F&F−1 class operations for 5G application

Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Meisam Tahmasbi ◽  
Farhad Razaghian ◽  
Sobhan Roshani
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
New Method ◽  
Power Added Efficiency ◽  
Hybrid Power ◽  
Novel Structure ◽  
Mode A

Abstract This paper presents a novel structure of Hybrid Power Amplifier (HPA) to operate in two arbitrary classes of operation at two desirable frequencies. The proposed HPA is designed in concurrent F&F−1 classes, simultaneously for 5G application. Presented HPA can solve the harmonics interference problem for concurrent F and F−1 classes and also for any arbitrary class of operation in desired frequencies. The designed HPA operates at 1.5 GHz frequency in the F class mode, while operates at 2.1 GHz frequency in the F−1 class mode. A new method is presented by using two diplexers to provide two paths for signal in different frequencies. Two parallel paths are used at the output of the HPA circuit, so the proposed HPA can operate at two classes. Two diplexers are used in the HPA to make proper isolation between the designed paths. In design of the proposed HPA, according to the utilized diplexers, the amplifier can operate between two arbitrary classes of operation at desired frequencies without any specific switch. The measured drain efficiency (DE) and power added efficiency (PAE) parameters are 57 and 51%, respectively at 2.1 GHz, while measured DE and PAE are 64 and 54%, respectively at 1.5 GHz.

scholarly journals Design of W-Band GaN-on-Silicon Power Amplifier Using Low Impedance Lines

2021 ◽  
Vol 11 (19) ◽  
pp. 9017
Author(s):  
Jinho Jeong ◽  
Yeongmin Jang ◽  
Jongyoun Kim ◽  
Sosu Kim ◽  
Wansik Kim
Keyword(s):  
Power Density ◽  
Output Power ◽  
Power Amplifier ◽  
High Power ◽  
Common Source ◽  
High Electron ◽  
Large Signal ◽  
Power Added Efficiency ◽  
W Band ◽  
Gan On Si

In this paper, a high-power amplifier integrated circuit (IC) in gallium-nitride (GaN) on silicon (Si) technology is presented at a W-band (75–110 GHz). In order to mitigate the losses caused by relatively high loss tangent of Si substrate compared to silicon carbide (SiC), low-impedance microstrip lines (20–30 Ω) are adopted in the impedance matching networks. They allow for the impedance transformation between 50 Ω and very low impedances of the wide-gate transistors used for high power generation. Each stage is matched to produce enough power to drive the next stage. A Lange coupler is employed to combine two three-stage common source amplifiers, providing high output power and good input/output return loss. The designed power amplifier IC was fabricated in the commercially available 60 nm GaN-on-Si high electron mobility transistor (HEMT) foundry. From on-wafer probe measurements, it exhibits the output power higher than 26.5 dBm and power added efficiency (PAE) higher than 8.5% from 88 to 93 GHz with a large-signal gain > 10.5 dB. Peak output power is measured to be 28.9 dBm with a PAE of 13.3% and a gain of 9.9 dB at 90 GHz, which corresponds to the power density of 1.94 W/mm. To the best of the authors’ knowledge, this result belongs to the highest output power and power density among the reported power amplifier ICs in GaN-on-Si HEMT technologies operating at the W-band.

A 2.4GHz Radio-Over-Fiber Laser Diode Drive Amplifier in 0.18-um CMOS

2013 ◽  
Vol 433-435 ◽  
pp. 1463-1469 ◽  
Author(s):  
Yi Lin Zheng ◽  
Ying Mei Chen ◽  
Jian Wei Gong ◽  
Jian Guo Yao
Keyword(s):  
Laser Diode ◽  
Cmos Technology ◽  
Radio Over Fiber ◽  
Power Gain ◽  
Power Added Efficiency ◽  
Input And Output ◽  
Linear Amplifier ◽  
Simulation Results ◽  
On Chip ◽  
Dynamic Bias

The design of a 2.4GHz radio-over-fiber (ROF) laser diode drive amplifier using TSMC 0.18-um CMOS technology is presented in this paper. The proposed drive amplifier is a single-ended two-stage amplifier with the operating voltages of 1.8V and 3.3V. The technique of dynamic bias is employed to enhance linearity. The post simulation results show that the linear amplifier achieves the power gain of 26.26dB, the output 1dB compression point of 20.49dBm at 2.4GHz. The maximum power added efficiency (PAE) is 27.97%. The components are all on chip including the input and output matching network, and the die size is 1.065mm×0.73mm.

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Premmilaah Gunasegaran ◽  
Jagadheswaran Rajendran ◽  
Selvakumar Mariappan ◽  
Yusman Mohd Yusof ◽  
Zulfiqar Ali Abdul Aziz ◽  
...  
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Power Amplifier ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Power Gain ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Main Amplifier

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

scholarly journals A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 69 ◽  
Author(s):  
Taufiq Alif Kurniawan ◽  
Toshihiko Yoshimasu
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Back Gate ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

Design of Broadband GaN HEMT Power Amplifier with Ku Band

2012 ◽  
Vol 263-266 ◽  
pp. 39-42 ◽  
Author(s):  
Zhi Qun Cheng ◽  
Li Wei Jin ◽  
Wen Shi
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Operating Conditions ◽  
Power Gain ◽  
Power Added Efficiency ◽  
Gan Hemt ◽  
Dc Bias ◽  
Simulation Results ◽  
Two Stages ◽  
Ku Band

A broadband power amplifier module based on GaN HEMT operating Ku band is designed. TGF2023-02 Chip of GaN HEMT from TriQuint is modeled first. And then the module consists of two stages amplifiers. The first stage amplifier is single-stage amplifier and the second is two-way combiner amplifier. Wilkinson power divider, DC bias circuits and microstrip matching circuits are simulated and designed carefully. Simulation results showed that the amplifier module exhibits a power gain of 7 dB, power added efficiency of 13.9%, and an output power of 16 W under Vds=28 V, Vgs=-3.6 V, CW operating conditions at the frequency of 15 GHz.

scholarly journals 0.5 GHz-1.5 GHz Bandwidth 10W GaN HEMT RF Power Amplifier Design

2018 ◽  
Vol 8 (3) ◽  
pp. 1837
Author(s):  
Shiva Ghandi Isma Ilamaran ◽  
Zubaida Yusoff ◽  
Jahariah Sampe
Keyword(s):  
Power Amplifier ◽  
Communication Technology ◽  
Rf Power ◽  
Power Added Efficiency ◽  
Rf Power Amplifier ◽  
Gan Hemt ◽  
Input And Output ◽  
Flat Gain ◽  
Amplifier Design ◽  
Load Pull

With the current development in wireless communication technology, the need for a wide bandwith in RF power amplifier (RF PA) is an essential. In this paper, the design and simulation of 10W GaN HEMT wideband RF PA will be presented. The Source-Pull and Load-Pull technique was used to design the input and output matching network of the RF PA. From the simulation, the RF PA achieved a flat gain between 15dB to 17dB from 0.5GHz to 1.5GHz. At 1.5GHz, the drain efficiency is simulated to achieve 36% at the output power of 40 dBm while the power added efficiency (PAE) was found to be 28.2%.

scholarly journals A trade-off design of microstrip broadband power amplifier for UHF applications

2020 ◽  
Vol 10 (1) ◽  
pp. 919
Author(s):  
Mohamed Ribate ◽  
Rachid Mandry ◽  
Jamal Zbitou ◽  
Larbi El Abdellaoui ◽  
Ahmed Errkik ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Transmission Lines ◽  
Impedance Matching ◽  
Wave Impedance ◽  
Large Signal ◽  
Active Device ◽  
Quarter Wave ◽  
Lumped Elements ◽  
Signal Simulation ◽  
Matching Techniques

In this paper, the design of a Broadband Power Amplifier for UHF applications is presented. The proposed BPA is based on ATF13876 Agilent active device. The biasing and matching networks both are implemented by using microstrip transmission lines. The input and output matching circuits are designed by combining two broadband matching techniques: a binomial multi-section quarter wave impedance transformer and an approximate transformation of previously designed lumped elements. The proposed BPA shows excellent performances in terms of impedance matching, power gain and unconditionally stability over the operating bandwidth ranging from 1.2 GHz to 3.3 GHz. At 2.2 GHz, the large signal simulation shows a saturated output power of 18.875 dBm with an output 1-dB compression point of 6.5 dBm of input level and a maximum PAE of 36.26%.

The Design and Modeling of 2.4 and 3.5 GHz MMIC PA

2012 ◽  
pp. 105-156
Author(s):  
Chin Guek Ang
Keyword(s):  
Power Amplifier ◽  
Wireless Lan ◽  
Return Loss ◽  
High Electron Mobility Transistor ◽  
Small Signal Gain ◽  
Small Signal ◽  
Signal Gain ◽  
Power Added Efficiency ◽  
Input And Output ◽  
Amplifier Design

This chapter discusses the design of MMIC power amplifiers for wireless application by using 0.15 µm GaAs Power Pseudomorphic High Electron Mobility Transistor (PHEMT) technology with a gate width of 100 µm and 10 fingers at 2.4 GHz and 3.5 GHz. The design methodology for power amplifier design can be broken down into three main sections: architecture design, small-signal design, and large-signal optimization. For 2.4 GHz power amplifier, with 3.0 V drain voltage, the amplifier has achieved 17.265 dB small-signal gain, input and output return loss of 16.310 dB and 14.418 dB, 14.862 dBm 1-dB compression power with 12.318% power-added efficiency (PAE). For 3.5GHz power amplifier, the amplifier has achieved 14.434 dB small-signal gain, input and output return loss of 12.612 dB and 11.746 dB, 14.665 dBm 1-dB compression power with 11.796% power-added efficiency (PAE). The 2.4 GHz power amplifier can be applied for Wireless LAN applications such as WiFi and WPAN whereas 3.5 GHz power amplifier for WiMax base station.

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