An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm2, including calibration.

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A Linearity Improved 10-bit 120-MS/s 1.5 mW SAR ADC with High-Speed and Low-Noise Dynamic Comparator Technique

Journal of Circuits System and Computers ◽

10.1142/s021812662050084x ◽

2019 ◽

Vol 29 (06) ◽

pp. 2050084

Author(s):

Daiguo Xu ◽

Hequan Jiang ◽

Dongbin Fu ◽

Xiaoquan Yu ◽

Shiliu Xu ◽

...

Keyword(s):

High Speed ◽

Cmos Technology ◽

Low Noise ◽

Sar Adc ◽

Dynamic Comparator ◽

Analog To Digital ◽

Input Noise ◽

Clock Feedthrough ◽

Threshold Voltages ◽

Coupled Technique

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5[Formula: see text]mW from 1[Formula: see text]V power supply with a SNDR [Formula: see text][Formula: see text]dB and SFDR [Formula: see text][Formula: see text]dB. The proposed ADC core occupies an active area of 0.021[Formula: see text]mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency.

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A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

Symmetry ◽

10.3390/sym12010165 ◽

2020 ◽

Vol 12 (1) ◽

pp. 165

Author(s):

Shouping Li ◽

Yang Guo ◽

Jianjun Chen ◽

Bin Liang

Keyword(s):

Successive Approximation ◽

High Speed ◽

Low Noise ◽

Digital Calibration ◽

Cmos Process ◽

Analog To Digital Converter ◽

Digital Converter ◽

Dynamic Comparator ◽

Analog To Digital ◽

Calibration Algorithm

This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

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A Low-Noise Dynamic Comparator with Offset Calibration for CMOS Image Sensor Architecture

Journal of Circuits System and Computers ◽

10.1142/s0218126619500221 ◽

2018 ◽

Vol 28 (02) ◽

pp. 1950022

Author(s):

Arumugam Sathishkumar ◽

Siddhan Saravanan

Keyword(s):

High Speed ◽

Cmos Image Sensor ◽

Image Sensor ◽

Low Noise ◽

Clock Frequency ◽

Dynamic Comparator ◽

Analog To Digital ◽

Input Capacitance ◽

Simulation Results ◽

Output Swing

A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-rail output swing is also improved. The input capacitance is reduced by using shared first-stage technique. The comparator is designed with constant [Formula: see text]/[Formula: see text] biasing to suppress the environmental drift. The simulation results from 45-nm and 65-nm CMOS technologies confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 3.5[Formula: see text]GHz and 2.2[Formula: see text]GHz at supply voltages of 1[Formula: see text]V and 0.6[Formula: see text]V, respectively. Simulations are carried out using predictive technology models for 45[Formula: see text]nm and 65[Formula: see text]nm in HSPICE.

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HSCT Forward Swept Fan Performance

Volume 6: Turbo Expo 2003, Parts A and B ◽

10.1115/gt2003-38948 ◽

2003 ◽

Author(s):

Robert J. Neubert ◽

Charles P. Gendrich

Keyword(s):

High Speed ◽

State Of The Art ◽

Low Noise ◽

Navier Stokes ◽

Light Weight ◽

Test Results ◽

Flow Solver ◽

Stall Margin ◽

Fan Performance ◽

Multi Stage

Previous experimental and analytical studies have demonstrated the potential for significant improvements in efficiency and stall margin with forward swept rotor blading. This paper extends the assessment to a light weight, low noise two stage fan designed and fabricated under the NASA High Speed Civil Transport program. The experimental investigation evaluates the effect of forward sweep on efficiency and stall margin relative to the predicted levels for a radial fan designed for the same requirements. Efficiency was above multi-stage fan state of the art and stall margin was significantly greater than predicted based on radial fan experience. In addition, the effects of increasing the axial gap between the IGV and rotor 1, as well as R1 to S1 axial gap are evaluated. The increased axial gap between R1 & S1 had a much greater effect on performance than increasing the IGV to R1 gap. And, 3D Navier-Stokes flow solver analysis was performed for comparison to test results.

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The High-Speed Low-Power Dynamic Comparator

Journal of Physics Conference Series ◽

10.1088/1742-6596/2113/1/012064 ◽

2021 ◽

Vol 2113 (1) ◽

pp. 012064

Author(s):

Menghua Cao ◽

Weixun Tang

Keyword(s):

Integrated Circuits ◽

Low Power ◽

Positive Feedback ◽

High Speed ◽

Low Noise ◽

Dynamic Comparator ◽

Low Delay ◽

Offset Voltage ◽

A Charge ◽

Definition Phase

Abstract This paper comments on four works for the optimization of comparator design. Today, with the development of integrated circuits, the requirements for comparators about low power, low delay, few offset voltage, and low noise are highly desirable. Specifically, these works made progress in the conventional comparator, which comprises a preamplifier and a latch. They also solved some problems, such as decreasing power and delay. Some works employ a positive feedback cross-coupled pares to provide a larger gain in the preamplifier, use PMOS switch transistors to accelerate the definition phase, or a double-tail architecture to increase the latch regeneration speed. Other work designs a charge pump to improve speed.

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A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2006.342249 ◽

2006 ◽

Cited By ~ 22

Author(s):

Vipul Katyal ◽

Randall L. Geiger ◽

Degang J. Chen

Keyword(s):

High Resolution ◽

High Precision ◽

High Speed ◽

Dynamic Comparator ◽

Low Offset

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Optically clocked track-and-hold for high-speed high-resolution analog-to-digital conversion

2004 IEEE International Topical Meeting on Microwave Photonics (IEEE Cat. No.04EX859) ◽

10.1109/mwp.2004.1396871 ◽

2005 ◽

Cited By ~ 7

Author(s):

E.W. Jacobs ◽

J.B. Sobti ◽

V.F. Vella ◽

R. Nguyen ◽

D.J. Albares ◽

...

Keyword(s):

High Resolution ◽

High Speed ◽

Digital Conversion ◽

Analog To Digital ◽

Analog To Digital Conversion

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Optically assisted high-speed, high resolution analog-to-digital conversion (Invited Paper)

10.1117/12.609863 ◽

2005 ◽

Cited By ~ 4

Author(s):

Henry Zmuda ◽

Shane Hanna ◽

R. J. Bussjager ◽

M. L. Fanto ◽

M. J. Hayduk ◽

...

Keyword(s):

High Resolution ◽

High Speed ◽

Digital Conversion ◽

Analog To Digital ◽

Analog To Digital Conversion

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High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime

International Journal of Nanoscience ◽

10.1142/s0219581x14500033 ◽

2014 ◽

Vol 13 (01) ◽

pp. 1450003

Author(s):

Bhanupriya Bhargava ◽

Pradeep Kumar Sharma ◽

Shyam Akashe

Keyword(s):

High Speed ◽

Flicker Noise ◽

Supply Voltage ◽

Frequency Noise ◽

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Op Amp ◽

Offset Voltage ◽

Delta Sigma

In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.

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