scholarly journals Memory Optimization for Bit-Vector-Based Packet Classification on FPGA

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1159 ◽  
Author(s):  
Chenglong Li ◽  
Tao Li ◽  
Junnan Li ◽  
Dagang Li ◽  
Hui Yang ◽  
...  
Keyword(s):  
High Throughput ◽  
High Performance ◽  
Classification Scheme ◽  
Packet Classification ◽  
Memory Consumption ◽  
The Past ◽  
Large Memory ◽  
Bit Vector ◽  
Memory Resources ◽  
Very High

High-performance packet classification algorithms have been widely studied during the past decade. Bit-Vector-based algorithms proposed for FPGA can achieve very high throughput by decomposing rules delicately. However, the relatively large memory resources consumption severely hinders applications of the algorithms extensively. It is noteworthy that, in the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively plenty of useless wildcards in the rules. We thus present a memory-optimized packet classification scheme named WeeBV to eliminate the memory occupied by the wildcards. WeeBV consists of a heterogeneous two-dimensional lookup pipeline and an optimized heuristic algorithm for searching all the wildcard positions that can be removed. It can achieve a significant reduction in memory resources without compromising the high throughput of the original Bit-Vector-based algorithms. We implement WeeBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can save 37% and 41% memory consumption on average for synthetic 5-tuple rules and OpenFlow rules respectively.

scholarly journals State of the Art: Mechanical Properties of Ultra-High Performance Concrete

2017 ◽  
Vol 3 (3) ◽  
pp. 190-198 ◽  
Author(s):  
Mohamadtaqi Baqersad ◽  
Ehsan Amir Sayyafi ◽  
Hamid Mortazavi Bak
Keyword(s):  
Mechanical Properties ◽  
High Performance ◽  
High Performance Concrete ◽  
State Of The Art ◽  
High Strength ◽  
Structural Members ◽  
Ultra High Performance Concrete ◽  
Conventional Concrete ◽  
The Past ◽  
Very High

During the past decades, there has been an extensive attention in using Ultra-High Performance Concrete (UHPC) in the buildings and infrastructures construction. Due to that, defining comprehensive mechanical properties of UHPC required to design structural members is worthwhile. The main difference of UHPC with the conventional concrete is the very high strength of UHPC, resulting designing elements with less weight and smaller sizes.  However, there have been no globally accepted UHPC properties to be implemented in the designing process. Therefore, in the current study, the UHPC mechanical properties such as compressive and tensile strength, modulus of elasticity and development length for designing purposes are provided based on the reviewed literature. According to that, the best-recommended properties of UHPC that can be used in designing of UHPC members are summarized. Finally, different topics for future works and researches on UHPC’s mechanical properties are suggested.

scholarly journals Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA

2020 ◽  
Vol 12 (8) ◽  
pp. 3068 ◽  
Author(s):  
Chenglong Li ◽  
Tao Li ◽  
Junnan Li ◽  
Zilin Shi ◽  
Baosheng Wang
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Recursive Algorithm ◽  
Packet Classification ◽  
Experimental Results ◽  
The Core ◽  
Core Function ◽  
Field Programmable ◽  
Bit Vector

Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

AFBV: A High-Performance Network Flow Classification Method for Multi-Dimensional Fields and FPGA Implementation

2019 ◽  
Vol 28 (14) ◽  
pp. 1950237
Author(s):  
Ling Zheng ◽  
Zhiliang Qiu ◽  
Weina Wang ◽  
Weitao Pan ◽  
Shiyong Sun ◽  
...  
Keyword(s):  
High Throughput ◽  
Network Flow ◽  
High Speed ◽  
High Performance ◽  
Clock Frequency ◽  
Pipeline Architecture ◽  
Exact Matching ◽  
Flow Classification ◽  
Rule Sets ◽  
Bit Vector

Network flow classification is a key function in high-speed switches and routers. It directly determines the performance of network devices. With the development of the Internet and various kinds of applications, the flow classification needs to support multi-dimensional fields, large rule sets, and sustain a high throughput. Software-based classification cannot meet the performance requirement as high as 100 Gbps. FPGA-based flow classification methods can achieve a very high throughput. However, the range matching is still challenging. For this, this paper proposes a range supported bit vector (RSBV) method. First, the characteristic of range matching is analyzed, then the rules are pre-encoded and stored in memory. Second, the fields of an input packet header are used as addresses to read the memory, and the result of range matching is derived through pipelined Boolean operations. On this basis, bit vector for any types of fields (AFBV) is further proposed, which supports the flow classification for multi-dimensional fields efficiently, including exact matching, longest prefix matching, range matching, and arbitrary wildcard matching. The proposed methods are implemented in FPGA platform. Through a two-dimensional pipeline architecture, the AFBV can operate at a high clock frequency and can achieve a processing speed of more than 100 Gbps. Simulation results show that for a rule set of 512-bit width and 1[Formula: see text]k rules, the AFBV can achieve a throughput of 520 million packets per second (MPPS). The performance is improved by 44% compared with FSBV and 30% compared with Stride BV. The power consumption is reduced by about 43% compared with TCAM solution.

scholarly journals Recognition of Handwritten Arabic and Hindi Numerals Using Convolutional Neural Networks

2021 ◽  
Vol 11 (4) ◽  
pp. 1573
Author(s):  
Amin Alqudah ◽  
Ali Mohammad Alqudah ◽  
Hiam Alquran ◽  
Hussein R. Al-Zoubi ◽  
Mohammed Al-Qodah ◽  
...  
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
High Performance ◽  
Recognition Rate ◽  
Second Stage ◽  
The Past ◽  
The World ◽  
Very High ◽  
Handwritten Arabic

Arabic and Hindi handwritten numeral detection and classification is one of the most popular fields in the automation research. It has many applications in different fields. Automatic detection and automatic classification of handwritten numerals have persistently received attention from researchers around the world due to the robotic revolution in the past decades. Therefore, many great efforts and contributions have been made to provide highly accurate detection and classification methodologies with high performance. In this paper, we propose a two-stage methodology for the detection and classification of Arabic and Hindi handwritten numerals. The classification was based on convolutional neural networks (CNNs). The first stage of the methodology is the detection of the input numeral to be either Arabic or Hindi. The second stage is to detect the input numeral according to the language it came from. The simulation results show very high performance; the recognition rate was close to 100%.

scholarly journals Tape Automated Bonding for High Density Packaging

1981 ◽  
Vol 8 (1-2) ◽  
pp. 15-19 ◽  
Author(s):  
Karel Kurzweil
Keyword(s):  
High Performance ◽  
Cost Effective ◽  
High Density ◽  
Electronic Systems ◽  
The Past ◽  
The World ◽  
Assembly Technology ◽  
Processing Steps ◽  
Very High ◽  
High Density Packaging

High density packaging of semiconductor devices is necessary for high performance in compact electronic systems. But the assembly technology must also remain cost attractive.Through the development efforts conducted during the past years in the world, the Tape Automated Bonding – TAB – has become the assembly technology allowing a very high density packaging. In combination with substrate technology it has grown into a complete, cost effective, micropackaging concept.The paper describes the main technical characteristics of this packaging concept. Specific equipments for TAB were designed and built by CII-Honeywell Bull for installation in the factory. These equipments are not only those, directly related to the TAB technology processing steps but include also other equipments like high precision thick film printer.The main features of the new micropackaging facility are also presented. Some examples of high density packages built with tape automated bonding are described and some of the main quality and reliability aspects are discussed.

scholarly journals A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos

2011 ◽  
Vol 2011 ◽  
pp. 1-9 ◽  
Author(s):  
Marcel M. Corrêa ◽  
Mateus T. Schoenknecht ◽  
Robson S. Dornelles ◽  
Luciano V. Agostini
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
High Throughput ◽  
High Performance ◽  
Hardware Architecture ◽  
Interpolation Process ◽  
High Definition ◽  
Efficient Search ◽  
Xilinx Fpga ◽  
Very High

This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV () in real time (30 frames per second). It also presents an optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The interpolation process is interleaved with the SAD calculation and comparison, allowing the high throughput. The architecture was fully described in VHDL, synthesized for two different Xilinx FPGA devices, and it achieved very good results when compared to related works.

scholarly journals High performance modified bit-vector based packet classification module on low-cost FPGA

2021 ◽  
Vol 11 (5) ◽  
pp. 3855
Author(s):  
Anita P. ◽  
Manju Devi
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Packet Classification ◽  
Total Power ◽  
Network Systems ◽  
Pipelined Architecture ◽  
Bit Vector ◽  
And Performance ◽  
Comparative Results ◽  
Application Requirements

The packet classification plays a significant role in many network systems, which requires the incoming packets to be categorized into different flows and must take specific actions as per functional and application requirements. The network system speed is continuously increasing, so the demand for the packet classifier also increased. Also, the packet classifier's complexity is increased further due to multiple fields should match against a large number of rules. In this manuscript, an efficient and high performance modified bitvector (MBV) based packet classification (PC) is designed and implemented on low-cost Artix-7 FPGA. The proposed MBV based PC employs pipelined architecture, which offers low latency and high throughput for PC. The MBV based PC utilizes <2% slices, operating at 493.102 MHz, and consumes 0.1 W total power on Artix-7 FPGA. The proposed PC considers only 4 clock cycles to classify the incoming packets and provides 74.95 Gbps throughput. The comparative results in terms of hardware utilization and performance efficiency of proposed work with existing similar PC approaches are analyzed with better constraints improvement.

KEMPER C688

Alloy Digest ◽  
2017 ◽  
Vol 66 (12) ◽  
Keyword(s):  
Corrosion Resistance ◽  
Physical Properties ◽  
Tensile Properties ◽  
Copper Alloy ◽  
High Performance ◽  
High Conductivity ◽  
Bend Strength ◽  
Very High

Abstract Alloy C688 is a high-performance copper alloy with very high conductivity. This datasheet provides information on composition, physical properties, hardness, elasticity, tensile properties, and bend strength. It also includes information on corrosion resistance as well as forming and joining. Filing Code: Cu-867. Producer or source: Gebr. Kemper GmbH + Company KG Metallwerke.

KEMPER KHP7025

Alloy Digest ◽  
2017 ◽  
Vol 66 (10) ◽  
Keyword(s):  
Corrosion Resistance ◽  
Physical Properties ◽  
Tensile Properties ◽  
Copper Alloy ◽  
High Performance ◽  
High Conductivity ◽  
Bend Strength ◽  
Very High

Abstract Alloy KHP 7025 (UNS C70250) is a high-performance copper alloy with very high conductivity. Uses include connector springs, tabs, contact springs, switches, relays, and leadframes. This datasheet provides information on composition, physical properties, hardness, elasticity, tensile properties, and bend strength. It also includes information on corrosion resistance as well as forming, machining, and joining. Filing Code: Cu-865. Producer or source: Gebr. Kemper GmbH + Company KG Metallwerke.

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