scholarly journals FPGA-Based Implementation of Finite Set-MPC for a VSI System Using XSG-Based Modeling

Energies ◽  
2020 ◽  
Vol 13 (1) ◽  
pp. 260 ◽  
Author(s):  
Vijay Kumar Singh ◽  
Ravi Nath Tripathi ◽  
Tsuyoshi Hanamoto
Keyword(s):  
Real Time ◽  
System Development ◽  
Control Strategies ◽  
System Modeling ◽  
Experimental System ◽  
Experimental Result ◽  
Voltage Source ◽  
Primary Concern ◽  
Fpga Design ◽  
Finite Set

Finite set-model predictive control (FS-MPC) is used for power converters and drives having unique advantages as compared to the conventional control strategies. However, the computational burden of the FS-MPC is a primary concern for real-time implementation. Field programmable gate array (FPGA) is an alternative and exciting solution for real-time implementation because of the parallel processing capability, as well as, discrete nature of the hardware platform. Nevertheless, FPGA is capable of handling the computational requirements for the FS-MPC implementation, however, the system development involves multiple steps that lead to the time-consuming debugging process. Moreover, specific hardware coding skill makes it more complex corresponding to an increase in system complexity that leads to a tedious task for system development. This paper presents an FPGA-based experimental implementation of FS-MPC using the system modeling approach. Furthermore, a comparative analysis of FS-MPC in stationary αβ and rotating dq frame is considered for simulation as well as experimental result. The FS-MPC for a three-phase voltage source inverter (VSI) system is developed in a realistic digital simulator integrated with MATLAB-Simulink. The simulated controller model is further used for experimental system implementation and validation using Xilinx FPGA: Zedboard Zynq Evaluation and Development Kit. The digital simulator termed as Xilinx system generator (XSG) provided by Xilinx is used for modeling-based FPGA design.

scholarly journals Real-Time Implementation of Robust Control Strategies Based on Sliding Mode Control for Standalone Microgrids Supplying Non-Linear Loads

Energies ◽  
2018 ◽  
Vol 11 (10) ◽  
pp. 2590 ◽  
Author(s):  
Seghir Benhalima ◽  
Rezkallah Miloud ◽  
Ambrish Chandra
Keyword(s):  
Sliding Mode Control ◽  
Real Time ◽  
Sliding Mode ◽  
Control Strategies ◽  
Storage System ◽  
Voltage Source ◽  
Voltage Source Converter ◽  
Sliding Mode Controller ◽  
Diesel Generator ◽  
Mode Control

In this paper enhanced control strategies for standalone microgrids based on solar photovoltaic systems (SVPAs) and diesel engine driven fixed speed synchronous generators, are presented. Single-phase d-q theory-based sliding mode controller for voltage source converter voltage source converter (VSC) is employed to mitigate harmonics, balance diesel generator (DG) current, and to inject the generated power by SVPA into local grid. To achieve fast dynamic response with zero steady-state error during transition, sliding mode controller for inner control loop is employed. To achieve maximum power point tracking (MPPT) from SVPA without using any MPPT method, a DC-DC buck boost converter supported by battery storage system is controlled using a new control strategy based on sliding mode control with boundary layer. In addition, modeling and detailed stability analysis are performed. The performance of the developed control strategies, are validate by simulation using MATLAB/Simulink and in real-time using hardware prototype.

scholarly journals Step-by-Step Development and Implementation of FS-MPC for a FPGA-Based PMSM Drive System

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 395
Author(s):  
Ipsita Mishra ◽  
Ravi Nath Tripathi ◽  
Vijay Kumar Singh ◽  
Tsuyoshi Hanamoto
Keyword(s):  
Real Time ◽  
System Development ◽  
Permanent Magnet Synchronous Motor ◽  
Harmonic Distortion ◽  
Current Control ◽  
Drive System ◽  
Motor Drive ◽  
Primary Concern ◽  
Depth Analysis ◽  
Motor Drive System

In this paper, finite-set model-predictive control (FS-MPC) is inducted for a motor drive system. The dynamic response and multiple constraint handling nature of FS-MPC are the major factors that stand out among the controller family. However, for real-time implementation, the computational burden of FS-MPC is a primary concern. Due to the parallel processing nature and discrete nature of the hardware platform, the field-programmable gate array (FPGA) can be an alternative solution for the real-time implementation of the controller algorithm. The FPGA is capable of handling the computational requirements for FS-MPC implementation; however, the system development involves multiple steps that lead to a time-consuming debugging process. Moreover, specific hardware coding skill makes it more complex, corresponding to an increase in system complexity, which leads to a tedious task for the system development. This paper presents a FPGA-based implementation of the predictive current control of a permanent magnet synchronous motor (PMSM). FS-MPC of the PMSM drive system is designed and implemented using the digital model integration approach provided by the Xilinx system generator (XSG) and VIVADO platform. The step change in the load disturbance as well as the reference speed is considered for the analysis of the controller for the motor drive system. Moreover, the steady state error and harmonic distortion in the motor current is considered for an in-depth analysis of the system performance corresponding to different sampling frequencies.

Real-Time Implementation of Type-2 FLC–Based Shunt Active Filter Control Strategies (p–q and Id–Iq) with Different Fuzzy MFs for Power Quality Improvement

2014 ◽  
Vol 15 (3) ◽  
pp. 217-236
Author(s):  
Suresh Mikkili ◽  
Anup Kumar Panda
Keyword(s):  
Real Time ◽  
Power Quality ◽  
Control Strategies ◽  
Voltage Regulation ◽  
Active Filter ◽  
Electrical Network ◽  
Voltage Source ◽  
Shunt Active Filter ◽  
Three Phase

Abstract This research article proposes the shunt active filter (SHAF) control strategies (p–q and Id–Iq), which are used to improve the power quality of the electrical network by mitigating the harmonics with the help of Type-2 fuzzy logic controller (Type-2 FLC) different membership functions (MFs). Three-phase reference current waveforms generated by proposed scheme are tracked by the three-phase voltage source converter in a hysteresis band control scheme. The performance of the proposed control strategies has been evaluated in terms of harmonic mitigation and DC link voltage regulation under various source conditions. In order to maintain DC link voltage constant and to generate the compensating reference currents, we have developed Type-2 FLC with different fuzzy MFs (trapezoidal, triangular and Gaussian). The SHAF with proposed Type-2 FLC using Gaussian MF is able to eliminate the uncertainty in the system and SHAF gains outstanding compensation abilities. The detailed real-time results using real-time digital simulator are presented to support the feasibility of proposed control strategies.

scholarly journals A New Experimental Method of Combined Fatigue of Actual Turbine Disk Mortise Teeth at Elevated Temperature

1996 ◽  
Author(s):  
Rongqiao Wang ◽  
Jingxu Nie
Keyword(s):  
Elevated Temperature ◽  
Experimental Method ◽  
Real Time ◽  
High Frequency ◽  
Local Heating ◽  
Experimental System ◽  
Turbine Disk ◽  
Combined Loading ◽  
Experimental Result ◽  
High Frequency Induction

For studying the L-HCCF of an actual turbine disk mortise teeth at elevated temperature, this paper presents a new experimental system, using actual disk as experimental component, ingeniously achieving the combined loading (simulating low cycle radial centrifugal force and high cycle crosswise vibration of blade), the high-frequency induction local heating (550 °C constant temperature), the control of high cycle vibrating frequency and amplitude, and the crack real-time detection. The experimental result is identical with the practical flight failure. This method can be easily popularized for the L-HCCF studying of many components.

Development and Application of Quality Control System for Highway Subgrade Construction

2019 ◽  
Vol 2 (5) ◽  
Author(s):  
Tong Wang
Keyword(s):  
Quality Control ◽  
Real Time ◽  
Detection Method ◽  
System Development ◽  
Effective Control ◽  
Construction Process ◽  
Development Mode ◽  
The Road ◽  
Whole Process

The compaction quality of the subgrade is directly related to the service life of the road. Effective control of the subgrade construction process is the key to ensuring the compaction quality of the subgrade. Therefore, real-time, comprehensive, rapid and accurate prediction of construction compaction quality through informatization detection method is an important guarantee for speeding up construction progress and ensuring subgrade compaction quality. Based on the function of the system, this paper puts forward the principle of system development and the development mode used in system development, and displays the development system in real-time to achieve the whole process control of subgrade construction quality.

Pollution based real time control strategies for combined sewer systems

1997 ◽  
Vol 36 (8-9) ◽  
pp. 331-336 ◽  
Author(s):  
Gabriela Weinreich ◽  
Wolfgang Schilling ◽  
Ane Birkely ◽  
Tallak Moland
Keyword(s):  
Real Time ◽  
Control Strategies ◽  
Ammonia Nitrogen ◽  
Simple Extension ◽  
Real Time Control ◽  
Time Control ◽  
Sewer Systems ◽  
Receiving Waters ◽  
Tunnel System

This paper presents results from an application of a newly developed simulation tool for pollution based real time control (PBRTC) of urban drainage systems. The Oslo interceptor tunnel is used as a case study. The paper focuses on the reduction of total phosphorus Ptot and ammonia-nitrogen NH4-N overflow loads into the receiving waters by means of optimized operation of the tunnel system. With PBRTC the total reduction of the Ptot load is 48% and of the NH4-N load 51%. Compared to the volume based RTC scenario the reductions are 11% and 15%, respectively. These further reductions could be achieved with a relatively simple extension of the operation strategy.

scholarly journals Power Hardware-in-the-Loop-Based Performance Analysis of Different Converter Controllers for Fast Active Power Regulation in Low-Inertia Power Systems

Energies ◽  
2021 ◽  
Vol 14 (11) ◽  
pp. 3274
Author(s):  
Jose Rueda Torres ◽  
Zameer Ahmad ◽  
Nidarshan Veera Kumar ◽  
Elyas Rakhshani ◽  
Ebrahim Adabi ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Power Systems ◽  
Real Time ◽  
Control Strategies ◽  
Active Power ◽  
Power Electronic ◽  
Hardware In The Loop ◽  
Digital Controllers ◽  
Power Regulation ◽  
The Impact

Future electrical power systems will be dominated by power electronic converters, which are deployed for the integration of renewable power plants, responsive demand, and different types of storage systems. The stability of such systems will strongly depend on the control strategies attached to the converters. In this context, laboratory-scale setups are becoming the key tools for prototyping and evaluating the performance and robustness of different converter technologies and control strategies. The performance evaluation of control strategies for dynamic frequency support using fast active power regulation (FAPR) requires the urgent development of a suitable power hardware-in-the-loop (PHIL) setup. In this paper, the most prominent emerging types of FAPR are selected and studied: droop-based FAPR, droop derivative-based FAPR, and virtual synchronous power (VSP)-based FAPR. A novel setup for PHIL-based performance evaluation of these strategies is proposed. The setup combines the advanced modeling and simulation functions of a real-time digital simulation platform (RTDS), an external programmable unit to implement the studied FAPR control strategies as digital controllers, and actual hardware. The hardware setup consists of a grid emulator to recreate the dynamic response as seen from the interface bus of the grid side converter of a power electronic-interfaced device (e.g., type-IV wind turbines), and a mockup voltage source converter (VSC, i.e., a device under test (DUT)). The DUT is virtually interfaced to one high-voltage bus of the electromagnetic transient (EMT) representation of a variant of the IEEE 9 bus test system, which has been modified to consider an operating condition with 52% of the total supply provided by wind power generation. The selected and programmed FAPR strategies are applied to the DUT, with the ultimate goal of ascertaining its feasibility and effectiveness with respect to the pure software-based EMT representation performed in real time. Particularly, the time-varying response of the active power injection by each FAPR control strategy and the impact on the instantaneous frequency excursions occurring in the frequency containment periods are analyzed. The performed tests show the degree of improvements on both the rate-of-change-of-frequency (RoCoF) and the maximum frequency excursion (e.g., nadir).

scholarly journals A Residual Network and FPGA Based Real-Time Depth Map Enhancement System

Entropy ◽  
2021 ◽  
Vol 23 (5) ◽  
pp. 546
Author(s):  
Zhenni Li ◽  
Haoyi Sun ◽  
Yuliang Gao ◽  
Jiao Wang
Keyword(s):  
Real Time ◽  
Super Resolution ◽  
Depth Map ◽  
Acquisition System ◽  
Depth Image ◽  
Fpga Design ◽  
Depth Sensing ◽  
Residual Network ◽  
Real Time Processing ◽  
Depth Maps

Depth maps obtained through sensors are often unsatisfactory because of their low-resolution and noise interference. In this paper, we propose a real-time depth map enhancement system based on a residual network which uses dual channels to process depth maps and intensity maps respectively and cancels the preprocessing process, and the algorithm proposed can achieve real-time processing speed at more than 30 fps. Furthermore, the FPGA design and implementation for depth sensing is also introduced. In this FPGA design, intensity image and depth image are captured by the dual-camera synchronous acquisition system as the input of neural network. Experiments on various depth map restoration shows our algorithms has better performance than existing LRMC, DE-CNN and DDTF algorithms on standard datasets and has a better depth map super-resolution, and our FPGA completed the test of the system to ensure that the data throughput of the USB 3.0 interface of the acquisition system is stable at 226 Mbps, and support dual-camera to work at full speed, that is, 54 fps@ (1280 × 960 + 328 × 248 × 3).

scholarly journals Power Hardware-in-the-Loop: Response of Power Components in Real-Time Grid Simulation Environment

Energies ◽  
2021 ◽  
Vol 14 (3) ◽  
pp. 593
Author(s):  
Moiz Muhammad ◽  
Holger Behrends ◽  
Stefan Geißendörfer ◽  
Karsten von Maydell ◽  
Carsten Agert
Keyword(s):  
Real Time ◽  
Power Distribution ◽  
Control Strategies ◽  
Power Grid ◽  
Energy System ◽  
Hardware In The Loop ◽  
Distribution Grid ◽  
Compensation Strategy ◽  
Software Environment ◽  
The Real

With increasing changes in the contemporary energy system, it becomes essential to test the autonomous control strategies for distributed energy resources in a controlled environment to investigate power grid stability. Power hardware-in-the-loop (PHIL) concept is an efficient approach for such evaluations in which a virtually simulated power grid is interfaced to a real hardware device. This strongly coupled software-hardware system introduces obstacles that need attention for smooth operation of the laboratory setup to validate robust control algorithms for decentralized grids. This paper presents a novel methodology and its implementation to develop a test-bench for a real-time PHIL simulation of a typical power distribution grid to study the dynamic behavior of the real power components in connection with the simulated grid. The application of hybrid simulation in a single software environment is realized to model the power grid which obviates the need to simulate the complete grid with a lower discretized sample-time. As an outcome, an environment is established interconnecting the virtual model to the real-world devices. The inaccuracies linked to the power components are examined at length and consequently a suitable compensation strategy is devised to improve the performance of the hardware under test (HUT). Finally, the compensation strategy is also validated through a simulation scenario.

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