Low Power QC-LDPC Decoder Based on Token Ring Architecture

The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

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LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

VLSI Design ◽

10.1155/2013/913018 ◽

2013 ◽

Vol 2013 ◽

pp. 1-14 ◽

Cited By ~ 4

Author(s):

Tinoosh Mohsenin ◽

Houshmand Shirani-mehr ◽

Bevan M. Baas

Keyword(s):

Low Power ◽

Energy Efficient ◽

State Of The Art ◽

Average Power ◽

Parity Check ◽

Ldpc Decoder ◽

Low Density Parity Check ◽

Variable Node ◽

Power Mode ◽

Ber Performance

An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6 lower than the state of the art reported power with an SNR loss of 0.35 dB at .

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A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications

The Scientific World JOURNAL ◽

10.1155/2015/327357 ◽

2015 ◽

Vol 2015 ◽

pp. 1-8

Author(s):

M. Revathy ◽

R. Saravanan

Keyword(s):

Low Power ◽

Low Complexity ◽

Fourth Generation ◽

Low Density ◽

Parity Check ◽

Ldpc Decoder ◽

Low Density Parity Check ◽

Variable Node ◽

High Efficient ◽

Decoder Architecture

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

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Improvement of Gain Accuracy and CMRR of Low Power Instrumentation Amplifier Using High Gain Operational Amplifiers

Micro and Nanosystems ◽

10.2174/1876402912666200123153318 ◽

2020 ◽

Vol 12 (3) ◽

pp. 168-174

Author(s):

Rashmi Sahu ◽

Maitraiyee Konar ◽

Sudip Kundu

Keyword(s):

Low Power ◽

Building Blocks ◽

High Gain ◽

The Other ◽

Operational Amplifiers ◽

Instrumentation Amplifier ◽

Biomedical Signals ◽

Op Amp ◽

Op Amps ◽

Multi Stage

Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.

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Clock Gating Implementation on commercial Field Programmable Gate Array (FPGA)

2018 4th International Conference on Electrical, Electronics and System Engineering (ICEESE) ◽

10.1109/iceese.2018.8703530 ◽

2018 ◽

Author(s):

Beng-Liong Tan ◽

Wai-Kong Lee ◽

Kai-Ming Mok ◽

Hock-Guan Goh

Keyword(s):

Field Programmable Gate Array ◽

Clock Gating ◽

Field Programmable ◽

Gate Array ◽

Commercial Field

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Field programmable gate array implementation of a generalized decoder for structured low-density parity check codes

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921) ◽

10.1109/fpt.2004.1393246 ◽

2005 ◽

Cited By ~ 5

Author(s):

Lingyan Sun ◽

B.V.K. Vijaya Kumar

Keyword(s):

Field Programmable Gate Array ◽

Low Density ◽

Parity Check ◽

Low Density Parity Check ◽

Field Programmable ◽

Gate Array ◽

Parity Check Codes

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Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

Electronics ◽

10.3390/electronics10010073 ◽

2021 ◽

Vol 10 (1) ◽

pp. 73

Author(s):

Francesco Ratto ◽

Tiziana Fanni ◽

Luigi Raffo ◽

Carlo Sau

Keyword(s):

Low Power ◽

Integrated Circuit ◽

Systems Design ◽

Hardware Acceleration ◽

High Level Synthesis ◽

Clock Gating ◽

Technology Application ◽

Positive Effects ◽

High Level ◽

Different Levels

With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

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A novel error correction protocol for continuous variable quantum key distribution

Scientific Reports ◽

10.1038/s41598-021-90055-3 ◽

2021 ◽

Vol 11 (1) ◽

Author(s):

Kadir Gümüş ◽

Tobias A. Eriksson ◽

Masahiro Takeoka ◽

Mikio Fujiwara ◽

Masahide Sasaki ◽

...

Keyword(s):

Error Correction ◽

Quantum Key Distribution ◽

Ldpc Codes ◽

Key Distribution ◽

Continuous Variable ◽

Early Termination ◽

Parity Check ◽

Secret Key ◽

Ldpc Decoder ◽

And Performance

AbstractReconciliation is a key element of continuous-variable quantum key distribution (CV-QKD) protocols, affecting both the complexity and performance of the entire system. During the reconciliation protocol, error correction is typically performed using low-density parity-check (LDPC) codes with a single decoding attempt. In this paper, we propose a modification to a conventional reconciliation protocol used in four-state protocol CV-QKD systems called the multiple decoding attempts (MDA) protocol. MDA uses multiple decoding attempts with LDPC codes, each attempt having fewer decoding iteration than the conventional protocol. Between each decoding attempt we propose to reveal information bits, which effectively lowers the code rate. MDA is shown to outperform the conventional protocol in regards to the secret key rate (SKR). A 10% decrease in frame error rate and an 8.5% increase in SKR are reported in this paper. A simple early termination for the LDPC decoder is also proposed and implemented. With early termination, MDA has decoding complexity similar to the conventional protocol while having an improved SKR.

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