scholarly journals Elimination of Unwanted Modes in Wavelength-Selective Uncooled Infrared Sensors with Plasmonic Metamaterial Absorbers using a Subtraction Operation

Materials ◽  
2019 ◽  
Vol 12 (19) ◽  
pp. 3157 ◽  
Author(s):  
Shinpei Ogawa ◽  
Yousuke Takagawa ◽  
Masafumi Kimata
Keyword(s):  
High Performance ◽  
Fire Detection ◽  
Complementary Metal Oxide Semiconductor ◽  
Single Mode ◽  
Gas Analysis ◽  
Oxide Semiconductor ◽  
Reference Pixel ◽  
Ir Sensors ◽  
Metamaterial Absorbers ◽  
Materials Used

Wavelength- or polarization-selective uncooled infrared (IR) sensors have various applications, such as in fire detection, gas analysis, hazardous material recognition, biological analysis, and polarimetric imaging. The unwanted modes originating due to the absorption by the materials used in these sensors, other than plasmonic metamaterial absorbers (PMAs), cause serious issues by degenerating the wavelength or polarization selectivity. In this study, we demonstrate a method for eliminating these unwanted modes in wavelength- or polarization-selective uncooled IR sensors with various PMAs, using a subtraction operation and a reference pixel. The aforementioned sensors and the reference pixels were fabricated using a complementary metal oxide semiconductor and micromachining techniques. We fabricated the reference pixel with the same structure as the PMA sensors, except a flat mirror was formed on the absorber surface instead of PMAs. The spectral responsivity measurements demonstrated that single-mode detection can be achieved through the subtraction operation with the reference pixel. The method demonstrated in this study can be applied to any type of uncooled IR sensors to create high-performance wavelength- or polarization-selective absorbers capable of multispectral or polarimetric detection.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Characterization of High-Performance Polycrystalline Silicon Complementary Metal–Oxide–Semiconductor Circuits

2007 ◽  
Vol 46 (1) ◽  
pp. 51-55 ◽  
Author(s):  
Genshiro Kawachi ◽  
Yoshiaki Nakazaki ◽  
Hiroyuki Ogawa ◽  
Masayuki Jyumonji ◽  
Noritaka Akita ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Polycrystalline Silicon ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Circuits

scholarly journals A Multiplexed Chemical Sensing CMOS Imager

2021 ◽  
Author(s):  
Di Wang ◽  
Fenni Zhang ◽  
Kyle Mallires ◽  
Vishal Tipparaju ◽  
Jingjing Yu ◽  
...  
Keyword(s):  
Chemical Sensing ◽  
High Performance ◽  
Health Management ◽  
Complementary Metal Oxide Semiconductor ◽  
Spot Size ◽  
Oxide Semiconductor ◽  
Colorimetric Sensing ◽  
Widespread Application ◽  
Cmos Imager ◽  
Cmos Chip

Abstract A miniaturized and multiplexed chemical sensing technology is urgently needed to empower mobile devices, Internet-of-Things (IoTs) and robots for various new applications. Here, we show that a complementary metal-oxide-semiconductor (CMOS) imager can be turned into a multiplexed colorimetric sensing chip by coating micron-scale colorimetric sensing spots on the imager surface. Each sensing spot contains chemical sensing materials and nanoparticles for colorimetric signal enhancement. The sensitivity is spot-size invariant, and high-performance chemical sensing can be achieved on sensing spot as small as ~ 10 µm. This great scalability combined with millions of pixels of a CMOS imager offers a promising platform for highly integrated chemical sensors. Moreover, the chemical CMOS chip can be readily integrated with mobile electronics. As a proof-of-concept, we have built a smartphone accessary based on this chemical CMOS chip for personal health management. We anticipate that this new platform will pave the way for the widespread application of chemical sensing, such as mobile health (mHealth), IoTs, electronic nose, and smart homes.

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Analog Complementary Metal–Oxide–Semiconductor Integrate-and-Fire Neuron Circuit for Overflow Retaining in Hardware Spiking Neural Networks

2020 ◽  
Vol 20 (5) ◽  
pp. 3117-3122
Author(s):  
Sungmin Hwang ◽  
Jeong-Jun Lee ◽  
Min-Woo Kwon ◽  
Myung-Hyun Baek ◽  
Taejin Jang ◽  
...  
Keyword(s):  
Neural Network ◽  
High Performance ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Basic Operation ◽  
Neuron Circuit ◽  
Integrate And Fire ◽  
Analog Cmos ◽  
High Level

The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized in upcoming high-performance hardware SNN systems.

Electromechanical Computing at 500°C with Silicon Carbide

Science ◽  
2010 ◽  
Vol 329 (5997) ◽  
pp. 1316-1318 ◽  
Author(s):  
Te-Hao Lee ◽  
Swarup Bhunia ◽  
Mehran Mehregany
Keyword(s):  
Silicon Carbide ◽  
Thermal Management ◽  
High Performance ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Propulsion Systems ◽  
Heat Sinking

Logic circuits capable of operating at high temperatures can alleviate expensive heat-sinking and thermal-management requirements of modern electronics and are enabling for advanced propulsion systems. Replacing existing complementary metal-oxide semiconductor field-effect transistors with silicon carbide (SiC) nanoelectromechanical system (NEMS) switches is a promising approach for low-power, high-performance logic operation at temperatures higher than 300°C, beyond the capability of conventional silicon technology. These switches are capable of achieving virtually zero off-state current, microwave operating frequencies, radiation hardness, and nanoscale dimensions. Here, we report a microfabricated electromechanical inverter with SiC complementary NEMS switches capable of operating at 500°C with ultralow leakage current.

scholarly journals Materials and processing approaches for foundry-compatible transient electronics

2017 ◽  
Vol 114 (28) ◽  
pp. E5522-E5529 ◽  
Author(s):  
Jan-Kai Chang ◽  
Hui Fang ◽  
Christopher A. Bower ◽  
Enming Song ◽  
Xinge Yu ◽  
...  
Keyword(s):  
Data Storage ◽  
Integrated Circuit ◽  
High Performance ◽  
Electronic Materials ◽  
Electronic Devices ◽  
Complementary Metal Oxide Semiconductor ◽  
Water Soluble ◽  
Oxide Semiconductor ◽  
Cost Structures ◽  
Functional Capabilities

Foundry-based routes to transient silicon electronic devices have the potential to serve as the manufacturing basis for “green” electronic devices, biodegradable implants, hardware secure data storage systems, and unrecoverable remote devices. This article introduces materials and processing approaches that enable state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) foundries to be leveraged for high-performance, water-soluble forms of electronics. The key elements are (i) collections of biodegradable electronic materials (e.g., silicon, tungsten, silicon nitride, silicon dioxide) and device architectures that are compatible with manufacturing procedures currently used in the integrated circuit industry, (ii) release schemes and transfer printing methods for integration of multiple ultrathin components formed in this way onto biodegradable polymer substrates, and (iii) planarization and metallization techniques to yield interconnected and fully functional systems. Various CMOS devices and circuit elements created in this fashion and detailed measurements of their electrical characteristics highlight the capabilities. Accelerated dissolution studies in aqueous environments reveal the chemical kinetics associated with the underlying transient behaviors. The results demonstrate the technical feasibility for using foundry-based routes to sophisticated forms of transient electronic devices, with functional capabilities and cost structures that could support diverse applications in the biomedical, military, industrial, and consumer industries.

High-Performance Current-Mode Logic Ternary D Flip-Flop Based on Bipolar Complementary Metal Oxide Semiconductor

2021 ◽  
Vol 16 (4) ◽  
pp. 528-533
Author(s):  
Xianghong Zhao ◽  
Longhua Ma ◽  
Hongye Su ◽  
Jieyu Zhao ◽  
Weiming Cai
Keyword(s):  
High Frequency ◽  
High Speed ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Oxide Semiconductor ◽  
Logic Function ◽  
Flip Flop ◽  
Current Mode Logic ◽  
Transmission Speed

In this paper, a simple-structured and high-performance current-mode logic (CML) ternary D flip-flop based on BiCMOS is proposed. It combines both advantages of BiCMOS and CML circuits, which is with much more high-speed, strong-drive and anti-interference abilities. Utilizing TSMC 180 nm process, results of simulations carried out by HSPICE illustrate the proposed circuit not only has correct logic function, but also gains improvements of 95.6~98.4% in average D-Q delay and 16.2%~70.4 in PDP compared with advanced ternary D flip-flop. When compared at the same information transmission speed, proposed circuit is more competitive. Furthermore, it can perform up to high frequency of 15 GHz and drive heavier load. All the results prove that proposed circuit is high-performance and very suitable for high-speed and high-frequency applications.

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