scholarly journals A 12-Bit 2.4 GS/s Four-Channel Pipelined ADC with a Novel On-Chip Timing Mismatch Calibration

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 910
Author(s):  
Hanbo Jia ◽  
Xuan Guo ◽  
Danyu Wu ◽  
Lei Zhou ◽  
Jian Luan ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Dynamic Performance ◽  
Sampling Rate ◽  
Detection Algorithm ◽  
Free Variable ◽  
Wide Frequency Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Mismatch Detection ◽  
On Chip

This paper presents a 12-bit 2.4 GS/s analog-to-digital converter (ADC) employing four time-interleaved (TI) pipelined channels with a novel on-chip timing mismatch calibration in 40 nm CMOS process. TI architecture can increase the effective sampling rate of ADC but the dynamic performance of TI-ADC system is seriously degraded by offset, gain, and timing mismatches among the channels. Timing mismatch is the most challenging barrier among these mismatches due to the difficulty and complexity of its detection and correction. An automatic wideband timing mismatch detection algorithm is proposed for achieving a wide frequency range of timing mismatch detection without complex calculations. By adopting the proposed mismatch-free variable delay line (VDL), the full-scale traversal timing mismatch correction accomplishes an accurate result without missing codes. Measurement results show that the spurious free dynamic range (SFDR) of the prototype ADC is improved from 55.2 dB to 72.8 dB after calibration at 2.4 GS/s with a 141 MHz input signal. It can achieve an SFDR above 60 dB across the entire first Nyquist band based on the timing mismatch calibration and retiming technology. The prototype ADC chip occupies an area of 3 mm × 3 mm and it consumes 420 mW from a 1.8 V supply.

scholarly journals A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3486
Author(s):  
Jae-Hun Lee ◽  
Dasom Park ◽  
Woojin Cho ◽  
Huu Phan ◽  
Cong Nguyen ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Dynamic Range ◽  
Sampling Error ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Calibration Technique ◽  
Accuracy Enhancement ◽  
On Chip ◽  
Comparator Offset

Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.

scholarly journals A Power-Efficient Pipelined ADC with an Inherent Linear 1-Bit Flip-Around DAC

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 199 ◽  
Author(s):  
Peiyuan Wan ◽  
Limei Su ◽  
Hongda Zhang ◽  
Zhijie Chen
Keyword(s):  
Dynamic Range ◽  
Low Voltage ◽  
Sampling Rate ◽  
Measured Signal ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Power Efficient ◽  
Sinusoidal Input ◽  
Bit Flip

An unity-gain 1-bit flip-around digital-to-analog converter (FADAC), without any capacitor matching issue, is proposed as the front-end input stage in a pipelined analog-to-digital converter (ADC), allowing an input signal voltage swing up to be doubled. This large input swing, coupled with the inherent large feedback factor (ideally β = 1) of the proposed FADAC, enables a power-efficient low-voltage high-resolution pipelined ADC design. The 1-bit FADAC is exploited in a SHA-less and opamp-sharing pipelined ADC, exhibiting 12-bit resolution with an input swing of 1.8 Vpp under a 1.1 V power supply. Fabricated in a 0.13-μm CMOS process, the prototype ADC achieves a measured signal-to-noise plus distortion ratio (SNDR) of 66.4 dB and a spurious-free dynamic range (SFDR) of 76.7 dB at 20 MS/s sampling rate. The ADC dissipates 5.2 mW of power and occupies an active area of 0.44 mm2. The measured differential nonlinearity (DNL) is +0.72/−0.52 least significant bit (LSB) and integral nonlinearity (INL) is +0.84/−0.75 LSB at a 3-MHz sinusoidal input.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

A ΣΔ MODULATOR USING GAIN-BOOST CLASS-C INVERTER FOR AUDIO APPLICATIONS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340024
Author(s):  
HAO LUO ◽  
YAN HAN ◽  
RAY C. C. CHEUNG ◽  
TIANLIN CAO ◽  
XIAOPENG LIU ◽  
...  
Keyword(s):  
High Resolution ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Signal To Noise ◽  
Dc Gain ◽  
Micro Power ◽  
Class C ◽  
On Chip ◽  
Σδ Modulator

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications.

scholarly journals A digital receiver signal strength detector for multi-standard low-IF receivers

2018 ◽  
Vol 16 ◽  
pp. 51-57
Author(s):  
Tobias Saalfeld ◽  
Tobias Piwczyk ◽  
Ralf Wunderlich ◽  
Stefan Heinen
Keyword(s):  
Dynamic Range ◽  
Computation Time ◽  
Signal Strength ◽  
Energy Detection ◽  
Cmos Technology ◽  
Detection Algorithm ◽  
Energy Consuming ◽  
Linearity Error ◽  
On Chip ◽  
Low If Receiver

Abstract. This paper presents a receiver signal strength detector based on a discrete Fourier transform implementation. The energy detection algorithm has been designed and measured using a custom multi-standard transceiver ASIC with a low-IF receiver at 0.5, 1 and 2 MHz IF. The proposed implementation directly processes the single bit ΔΣ modulator data and features a clear channel assessment for arbitrary modulation schemes without energy consuming demodulation. Continuous monitoring of the derivative of the RSSI takes advantage of faster coefficient convergence for higher power levels and reduces computation time. A dynamic range of 65 dB has been achieved in FPGA based measurements with a linearity error of less than 1.2 dB. Furthermore, synthesis results for an on-chip implementation for an 130 nm RF CMOS technology show an overall power consumption of 1.5 mW during calculation.

A VERY LOW POWER BANDPASS FILTER FOR LOW-IF APPLICATIONS

2008 ◽  
Vol 17 (04) ◽  
pp. 685-701 ◽  
Author(s):  
Gh. ZAREH FATIN ◽  
Z. D. KOOZEH KANANI
Keyword(s):  
Bandpass Filter ◽  
Dynamic Range ◽  
Second Order ◽  
Center Frequency ◽  
Cmos Process ◽  
Considerable Saving ◽  
Biquad Filter ◽  
External Reference ◽  
On Chip ◽  
Order Structures

This paper presents a second-order bandpass filter for IF frequencies in the range of 500 kHz–2 MHz. By using a single Gm–cell as a biquad filter, considerable saving in area and power is feasible. Higher order structures can be achieved by cascading this second-order block. This Gm-C filter achieves a dynamic range of 37 dB for 1% IM3 in Bluetooth while dissipating only 10.5 mW from 3.3 power supply in 0.35 μm CMOS process. The on-chip indirect automatic tuning circuit sets the filter center frequency to an external reference clock.

scholarly journals Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 872 ◽  
Author(s):  
Khuram Shehzad ◽  
Deeksha Verma ◽  
Danial Khan ◽  
Qurat Ain ◽  
Muhammad Basim ◽  
...  
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Sampling Rate ◽  
Reference Voltage ◽  
Cmos Process ◽  
Control Logic ◽  
Process Technology ◽  
Voltage Generator ◽  
Switching Energy ◽  
On Chip

This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.

A High Speed Open-Loop Track/Hold Circuit in CMOS Process

2013 ◽  
Vol 756-759 ◽  
pp. 4302-4305
Author(s):  
Zheng Ping Zhang ◽  
Yong Lu Wang ◽  
Ming Liu
Keyword(s):  
High Speed ◽  
Dynamic Range ◽  
Sampling Rate ◽  
Open Loop ◽  
Cmos Process ◽  
High Sampling ◽  
High Sampling Rate ◽  
Interleaved Structure ◽  
Offset Compensation ◽  
Loop Track

A high speed open-loop track/hold circuit in 0.18um CMOS process is presented. Open-loop and differential architecture are adopted to obtain high bandwidth and high speed;time-interleaved structure is used to reach a high sampling rate;source negative feedback and offset compensation are used to improve the linearity of the circuit.Simulation results show that with 396.875MHz input, 1.6GSPS sampling rate, driving the pre-amplifier of ADC, the thack/hold circuits SFDR(spurious-free dynamic range) is 75.8dB,satisfying the demand of 12 bits ADC.The circuit features high sampling rate,wide bandwidth,high SFDR and universal.

scholarly journals A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC using Simultaneous Capacitor and Op-amp Sharing Technique

2021 ◽  
Author(s):  
Shylu Sam ◽  
D. Jackuline Moni ◽  
P.Sam Paul ◽  
D. Nirmal
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Effective Number ◽  
Op Amp ◽  
Integral Nonlinearity ◽  
Silicon Based ◽  
Variable G

Abstract This work presents a low power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in a 180nm silicon based CMOS process. Simultaneous capacitor sharing and op-amp sharing technique is used between two successive stages of a Sample-and Hold Ampifier (SHA) to reduce the power consumption.The memory effect in the proposed ADC is eliminated by a low input capacitance variable gm op-amp. The differential and integral nonlinearity of the converter are within LSB.Simulation results show that the required Signal-Furious-Dynamic range (SFDR) of 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) of 56.1dB and 9.02 Effective Number of Bits ( ENOB ) has been achieved with a 2MHz, 1-Vp−p,diff input signal while consuming only 7.3mW power from 1.8V supply.

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