scholarly journals SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 5 ◽  
Author(s):  
Georgios Ioannis Paliaroutis ◽  
Pelopidas Tsoumanis ◽  
Nestor Evmorfopoulos ◽  
George Dimitriou ◽  
Georgios I. Stamoulis
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Research Field ◽  
Soft Error ◽  
Transient Faults ◽  
Simulation Based ◽  
Radiation Induced ◽  
The Impact ◽  
Pulse Characterization

Integrated circuit susceptibility to radiation-induced faults remains a major reliability concern. The continuous downscaling of device feature size and the reduction in supply voltage in CMOS technology tend to worsen the problem. Thus, the evaluation of Soft Error Rate (SER) in the presence of multiple transient faults is necessary, since it remains an open research field. In this work, a Monte-Carlo simulation-based methodology is presented taking into consideration the masking mechanisms and placement information. The proposed SER estimation tool exploits the results of a Single Event Transient (SET) pulse characterization process with HSPICE to obtain an accurate assessment of circuit vulnerability to radiation. A new metric, called Glitch Latching Probability, which represents the impact of the masking effects on a SET, is introduced to identify gate sensitivity and, finally, experimental results on a set of ISCAS’ 89 benchmarks are presented.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

scholarly journals A VCII-Based Stray Insensitive Analog Interface for Differential Capacitance Sensors

Sensors ◽  
2019 ◽  
Vol 19 (16) ◽  
pp. 3545 ◽  
Author(s):  
Gianluca Barile ◽  
Leila Safari ◽  
Giuseppe Ferri ◽  
Vincenzo Stornelli
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Differential Capacitance ◽  
Discrete Version ◽  
Capacitive Sensors ◽  
Active Devices ◽  
Novel Approach ◽  
Circuit Fabrication

In this paper, a novel approach to implement a stray insensitive CMOS interface for differential capacitive sensors is presented. The proposed circuit employs, for the first time, second-generation voltage conveyors (VCIIs) and produces an output voltage proportional to differential capacitor changes. Using VCIIs as active devices inherently allows the circuit to process the signal in the current domain, and hence, to benefit from its intrinsic advantages, such as high speed and simple implementation, while still being able to natively interface with voltage mode signal processing stages at necessity. The insensitiveness to the effects of parasitic capacitances is achieved through a simple feedback loop. In addition, the proposed circuit shows a very simple and switch-free structure (which can be used for both linear and hyperbolic sensors), improving its accuracy. The readout circuit was designed in a standard 0.35 μm CMOS technology under a supply voltage of ±1.65 V. Before the integrated circuit fabrication, to produce tangible proof of the effectiveness of the proposed architecture, a discrete version of the circuit was also prototyped using AD844 and LF411 to implement a discrete VCII. The achieved measurement results are in good agreement with theory and simulations, showing a constant sensitivity up to 412 mV/pF, a maximum linearity error of 1.9%FS, and acknowledging a good behavior with low baseline capacitive sensors (10 pF in the proposed measurements). A final table is also given to summarize the key specs of the proposed work comparing them to the available literature.

Genetic Algorithm-based Reliability Optimization for High-Level Synthesis

2019 ◽  
Vol 28 (03) ◽  
pp. 1950039 ◽  
Author(s):  
Suleyman Tosun ◽  
Tohid Taghizad Gogjeh Yaran
Keyword(s):  
Genetic Algorithm ◽  
Integrated Circuits ◽  
Radiation Effects ◽  
Supply Voltage ◽  
Heuristic Method ◽  
Cmos Technology ◽  
Error Correcting Codes ◽  
Error Rates ◽  
Soft Error ◽  
Final Design

Soft errors (SEs) are a type of transient errors in integrated circuits (ICs) caused by radiation effects in the chips. They have become the major concern in IC design process in each CMOS technology generation since the decrease in supply voltage levels for shrinking transistor sizes makes the circuits more vulnerable than before. Previous studies generally use hardware redundancy for combinational circuits and error correcting codes for memory elements to mitigate or eliminate the SEs. However, adding extra hardware in final design may not always be possible if the design has tight area constraints. Different implementations of the same function may have different soft error rates (SERs) due to their error masking capabilities. Therefore, we can obtain various versions of the same function with different area, latency, and reliability values. Allocating the best resources to the operations of the design under area and latency constraints to optimize the overall system reliability has NP-complete time complexity. Evolutionary computing-based methods suit very well for this optimization problem. Motivated by this fact, in this paper, we present a genetic algorithm (GA)-based design method to increase the reliability of application-specific integrated circuits (ASICs). In this method, we use different versions of the same resources, each having a different area, latency, and reliability values. The goal of the GA-based optimizer is to allocate the best available resources to the application nodes to maximize the reliability of the design under tight area and latency constraints. Our experimental results show that we achieve up to 20.86% reliability improvement against a heuristic method with no additional area overhead. In order to further increase the reliability of the final design, we also propose a heuristic-based post-processing method, which adds duplicate resources to the final design without violating the constraint.

scholarly journals Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1256
Author(s):  
Seyedehsomayeh Hatefinasab ◽  
Noel Rodriguez ◽  
Antonio García ◽  
Encarnacion Castillo
Keyword(s):  
Standard Deviation ◽  
Power Consumption ◽  
Threshold Voltage ◽  
Low Cost ◽  
Process Variations ◽  
Cmos Technology ◽  
Soft Error ◽  
Single Event ◽  
Power Delay Product ◽  
The Impact

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%.

scholarly journals Resilient Soft-Error Endurable Latch Design

2019 ◽  
Vol 8 (6) ◽  
pp. 759-768
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Ground Level ◽  
Radiation Energy ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Soft Error ◽  
Radiation Environment ◽  
Transient Faults ◽  
Circuit Output

Errors may occur in the circuit output because of upset in the stored or communicated charge. Such errors are considered as Transient Faults. The Transient Fault (TF) causes the soft error in the circuit output. So, designing of the latches which are unsusceptible to the Transient Faults disregarding the hitting particles energy is proposed in this project. Traditionally the soft-error based VLSI is limited to applications which require high reliability and operated in high radiation environment such as avionics applications, medical equipments, space industry and military applications. However, CMOS technology scales down to nanometre region, VLSI circuits also get affected by soft errors at ground level which features low radiation energy. Here, in this paper, totally three soft error tolerant latch designs are proposed, which includes High Performance, low cost and resilient soft error endurable latch, HLR-CG, HLR-CG1 and modified HLR-CG1. The proposed designs achieve better reliability with lower power consumption, delay, power delay product and area. The latches proposed are implemented in 45 nm technology and 32 nm technologies.

scholarly journals Design of Signal Generators Using Active Elements Developed in I3T25 CMOS Technology Single IC Package for Illuminance to Frequency Conversion

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1198
Author(s):  
Roman Sotner ◽  
Jan Jerabek ◽  
Ladislav Polak ◽  
Vilem Kledrowetz ◽  
Roman Prokop
Keyword(s):  
Integrated Circuit ◽  
Frequency Conversion ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
Cmos Technology ◽  
Bias Current ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Driving Voltage ◽  
Ic Package

This paper presents a compact and simple design of adjustable triangular and square wave functional generators employing fundamental cells fabricated on a single integrated circuit (IC) package. Two solutions have electronically tunable repeating frequency. The linear adjustability of repeating frequency was verified in the range between 17 and 264 kHz. The main benefits of the proposed generator are the follows: A simple adjustment of the repeating frequency by DC bias current, Schmitt trigger (threshold voltages) setting by DC driving voltage, and output levels in hundreds of mV when the complementary metal-oxide semiconductor (CMOS) process with limited supply voltage levels is used. These generators are suitable to provide a simple conversion of illuminance to frequency of oscillation that can be employed for illuminance measurement and sensing in the agriculture applications. Experimental measurements proved that the proposed concept is usable for sensing of illuminance in the range from 1 up to 500 lx. The change of illuminance within this range causes driving of bias current between 21 and 52 μA that adjusts repeating frequency between 70 and 154 kHz with an error up to 10% between the expected and real cases.

scholarly journals A New Simulated Inductor with Reduced Series Resistor Using a Single VCII±

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1693
Author(s):  
Erkan Yuce ◽  
Leila Safari ◽  
Shahram Minaei ◽  
Giuseppe Ferri ◽  
Gianluca Barile ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Low Frequency ◽  
Matching Condition ◽  
Cmos Technology ◽  
Passive Component ◽  
Component Matching ◽  
Series Resistor ◽  
Cmos Implementation ◽  
Fifth Order

This paper presents a new realization of a grounded simulated inductor using a single dual output second-generation voltage conveyor (VCII±) as an active building block, two resistors and one grounded capacitor. The main characteristic of the proposed circuit is that the value of the series resistor can be significantly reduced. Thus, it has the property of improved low-frequency performance. Another feature is the use of a grounded capacitor that makes the proposed circuit attractive for integrated circuit (IC) realization. A simple CMOS implementation of the required VCII± is used. However, a single passive component-matching condition is required for the proposed structure. As an application example, a standard fifth-order high-pass ladder filter is also given. SPICE simulations using 0.18 μm CMOS technology parameters and a supply voltage of ±0.9 V as well as experimental verifications, are carried out to support the theory.

Enhancement in Retention Time of 3TDRAM Using Double Gate Finfet Technology at Nanometer Regime.

2021 ◽  
pp. 359-370
Author(s):  
Amol S. Sankpala, D. J. Peteb
Keyword(s):  
Leakage Current ◽  
Retention Time ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Average Power ◽  
Random Access ◽  
Cmos Technology ◽  
Double Gate ◽  
Silicon Area ◽  
Nanometer Regime

Leakage current, power and area is the key challenges for VLSI designer during implementation of low power devices. In an integrated circuit number of transistors double in small silicon area every two years. There are certain limitations of cmos technology in nanometer regime out of which leakage current, leakage power, average current and average power is an important issues. In this paper, Retention time improvement in three transistor dynamic random access memory using double gate Finfet technology is proposed. Double gate finfet technology in 3TDRAM overcomes the issues related to cmos technology and it does not required additional circuitry. Proposed 3T DRAM is investigated with cmos and finfet technology at 90nm technology using cadence tool. Analysis of 3TDRAM using cmos and double gate finfet technology is carried out by variation in supply voltage and capacitance values. In double gate finfet technology leakage parameters are minimized and retention time(Th) is more improved as compared to cmos technology is observed.

scholarly journals Linearity improvement of differential CMOS low noise amplifier

2019 ◽  
Vol 14 (1) ◽  
pp. 407
Author(s):  
Maizan Muhamad ◽  
Norhayati Soin ◽  
Harikrishnan Ramiah
Keyword(s):  
Integrated Circuit ◽  
Wireless Lan ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Linearity Improvement ◽  
Noise Amplifier

<p>This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S<sub>21</sub> gain of 18.56 dB, noise figure (NF) of 1.85 dB, S<sub>11</sub> of −27.63 dB, S<sub>22</sub> of -34.33 dB, S<sub>12</sub> of −37.09 dB and IIP3 of -7.79 dBm.</p>

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