scholarly journals A Novel Low-Power Encryption Scheme Based on Chaotic Dynamic Triple Pendulum System for Wide Range of Applications

2021 ◽  
Author(s):  
Bikram Paul
Keyword(s):  
Low Power ◽  
Quantum Computer ◽  
Chaotic Dynamic ◽  
Average Power ◽  
Encryption Scheme ◽  
Security Threat ◽  
Pendulum System ◽  
Randomness Test ◽  
Triple Pendulum ◽  
Wide Range

<div>Recent advancements in the domain of quantum computing are posing a security threat to the classical cryptography algorithms. Popular symmetric and asymmetric cryptosystems including RSA, ECC, DES, Diffie-Hellman etc. can be broken by a quantum computer executing Shors and Grovers algorithms. This motivated scientific community to design newer encryption schemes to address security vulnerabilities. Hash, Code, Lattice, Multivariate Polynomial based cryptography algorithms, known as post-quantum cryptography algorithms (PQC), exhibit resistance against classical as well as quantum crypto-attacks. Apart from these PQC algorithms, a relatively new method of constructing cryptosystems utilizing the unpredictability property of discrete chaotic dynamic systems has become noteworthy from the practical perspective. In this paper, we present a novel approach to design an encryption scheme based on the chaotic dynamic physical system, which is derived from a mechanical model depicting nonlinear dynamics and exhibits resistance against various attacks. The effectiveness of the proposed cryptography scheme is validated against various standard tests, such as Lyapunov exponents test, bifurcation diagrams, sensitivity to parametric and to initial values, ergodicity, collision test, NIST, diehard randomness test etc. This algorithm is also verified through an FPGA implementation to assess its usage in low power high throughput applications as well. The power consumption and resource utilization of the proposed design are 56 % and 72.6 %, respectively, as compared to other known methods while operating at 628.14 MHz. It is observed that the proposed design can work efficiently with various wide range of applications. It is observed that the proposed design can work efficiently with various wide range of applications. The average power and area of its ASIC implementation at 180 nm technology are 61.8836 mW and 0.20374 mm 2 at 250 MHz, respectively.</div>

scholarly journals A Novel Low-Power Encryption Scheme Based on Chaotic Dynamic Triple Pendulum System for Wide Range of Applications

2021 ◽  
Author(s):  
Bikram Paul
Keyword(s):  
Low Power ◽  
Quantum Computer ◽  
Chaotic Dynamic ◽  
Average Power ◽  
Encryption Scheme ◽  
Security Threat ◽  
Pendulum System ◽  
Randomness Test ◽  
Triple Pendulum ◽  
Wide Range

<div>Recent advancements in the domain of quantum computing are posing a security threat to the classical cryptography algorithms. Popular symmetric and asymmetric cryptosystems including RSA, ECC, DES, Diffie-Hellman etc. can be broken by a quantum computer executing Shors and Grovers algorithms. This motivated scientific community to design newer encryption schemes to address security vulnerabilities. Hash, Code, Lattice, Multivariate Polynomial based cryptography algorithms, known as post-quantum cryptography algorithms (PQC), exhibit resistance against classical as well as quantum crypto-attacks. Apart from these PQC algorithms, a relatively new method of constructing cryptosystems utilizing the unpredictability property of discrete chaotic dynamic systems has become noteworthy from the practical perspective. In this paper, we present a novel approach to design an encryption scheme based on the chaotic dynamic physical system, which is derived from a mechanical model depicting nonlinear dynamics and exhibits resistance against various attacks. The effectiveness of the proposed cryptography scheme is validated against various standard tests, such as Lyapunov exponents test, bifurcation diagrams, sensitivity to parametric and to initial values, ergodicity, collision test, NIST, diehard randomness test etc. This algorithm is also verified through an FPGA implementation to assess its usage in low power high throughput applications as well. The power consumption and resource utilization of the proposed design are 56 % and 72.6 %, respectively, as compared to other known methods while operating at 628.14 MHz. It is observed that the proposed design can work efficiently with various wide range of applications. It is observed that the proposed design can work efficiently with various wide range of applications. The average power and area of its ASIC implementation at 180 nm technology are 61.8836 mW and 0.20374 mm 2 at 250 MHz, respectively.</div>

scholarly journals Low Power Cusped Field Thruster Developed for the Space-Borne Gravitational Wave Detection Mission in China

2021 ◽  
Vol 11 (14) ◽  
pp. 6549
Author(s):  
Hui Liu ◽  
Ming Zeng ◽  
Xiang Niu ◽  
Hongyan Huang ◽  
Daren Yu
Keyword(s):  
Low Power ◽  
Gravitational Wave ◽  
Attitude Control ◽  
High Efficiency ◽  
Experimental Investigations ◽  
Attitude Control System ◽  
Gravitational Wave Detection ◽  
Wave Detection ◽  
Wide Range ◽  
Institute Of Technology

The microthruster is the crucial device of the drag-free attitude control system, essential for the space-borne gravitational wave detection mission. The cusped field thruster (also called the High Efficiency Multistage Plasma Thruster) becomes one of the candidate thrusters for the mission due to its low complexity and potential long life over a wide range of thrust. However, the prescribed minimum of thrust and thrust noise are considerable obstacles to downscaling works on cusped field thrusters. This article reviews the development of the low power cusped field thruster at the Harbin Institute of Technology since 2012, including the design of prototypes, experimental investigations and simulation studies. Progress has been made on the downscaling of cusped field thrusters, and a new concept of microwave discharge cusped field thruster has been introduced.

scholarly journals Design of a high-stability heterogeneous clock system for small satellites in LEO

GPS Solutions ◽  
2021 ◽  
Vol 25 (3) ◽  
Author(s):  
Damon Van Buren ◽  
Penina Axelrad ◽  
Scott Palo
Keyword(s):  
Low Power ◽  
High Stability ◽  
Time Frame ◽  
System Stability ◽  
Small Satellite ◽  
Crystal Oscillator ◽  
Small Satellites ◽  
Clock System ◽  
Wide Range

AbstractWe describe our investigation into the performance of low-power heterogeneous timing systems for small satellites, using real GPS observables from the GRACE Follow-On mission. Small satellites have become capable platforms for a wide range of commercial, scientific and defense missions, but they are still unable to meet the needs of missions that require precise timing, on the order of a few nanoseconds. Improved low-power onboard clocks would make small satellites a viable option for even more missions, enabling radio aperture interferometry, improved radio occultation measurements, high altitude GPS navigation, and GPS augmentation missions, among others. One approach for providing improved small satellite timekeeping is to combine a heterogeneous group of oscillators, each of which provides the best stability over a different time frame. A hardware architecture that uses a single-crystal oscillator, one or more Chip Scale Atomic Clocks (CSACs) and the reference time from a GPS receiver is presented. The clocks each contribute stability over a subset of timeframes, resulting in excellent overall system stability for timeframes ranging from less than a second to several days. A Kalman filter is used to estimate the long-term errors of the CSACs based on the CSAC-GPS time difference, and the improved CSAC time is used to discipline the crystal oscillator, which provides the high-stability reference clock for the small satellite. Simulations using GRACE-FO observations show time error standard deviations for the system range from 2.3 ns down to 1.3 ns for the clock system, depending on how many CSACs are used. The results provide insight into the timing performance which could be achieved on small LEO spacecraft by a low power timing system.

Binary Precision Neural Network Manycore Accelerator

2021 ◽  
Vol 17 (2) ◽  
pp. 1-27
Author(s):  
Morteza Hosseini ◽  
Tinoosh Mohsenin
Keyword(s):  
Neural Network ◽  
Low Power ◽  
Image Classification ◽  
Case Studies ◽  
Average Power ◽  
Total Power ◽  
Fabrication Technology ◽  
Population Count ◽  
Cluster Architecture ◽  
Domain Specific

This article presents a low-power, programmable, domain-specific manycore accelerator, Binarized neural Network Manycore Accelerator (BiNMAC), which adopts and efficiently executes binary precision weight/activation neural network models. Such networks have compact models in which weights are constrained to only 1 bit and can be packed several in one memory entry that minimizes memory footprint to its finest. Packing weights also facilitates executing single instruction, multiple data with simple circuitry that allows maximizing performance and efficiency. The proposed BiNMAC has light-weight cores that support domain-specific instructions, and a router-based memory access architecture that helps with efficient implementation of layers in binary precision weight/activation neural networks of proper size. With only 3.73% and 1.98% area and average power overhead, respectively, novel instructions such as Combined Population-Count-XNOR , Patch-Select , and Bit-based Accumulation are added to the instruction set architecture of the BiNMAC, each of which replaces execution cycles of frequently used functions with 1 clock cycle that otherwise would have taken 54, 4, and 3 clock cycles, respectively. Additionally, customized logic is added to every core to transpose 16×16-bit blocks of memory on a bit-level basis, that expedites reshaping intermediate data to be well-aligned for bitwise operations. A 64-cluster architecture of the BiNMAC is fully placed and routed in 65-nm TSMC CMOS technology, where a single cluster occupies an area of 0.53 mm 2 with an average power of 232 mW at 1-GHz clock frequency and 1.1 V. The 64-cluster architecture takes 36.5 mm 2 area and, if fully exploited, consumes a total power of 16.4 W and can perform 1,360 Giga Operations Per Second (GOPS) while providing full programmability. To demonstrate its scalability, four binarized case studies including ResNet-20 and LeNet-5 for high-performance image classification, as well as a ConvNet and a multilayer perceptron for low-power physiological applications were implemented on BiNMAC. The implementation results indicate that the population-count instruction alone can expedite the performance by approximately 5×. When other new instructions are added to a RISC machine with existing population-count instruction, the performance is increased by 58% on average. To compare the performance of the BiNMAC with other commercial-off-the-shelf platforms, the case studies with their double-precision floating-point models are also implemented on the NVIDIA Jetson TX2 SoC (CPU+GPU). The results indicate that, within a margin of ∼2.1%--9.5% accuracy loss, BiNMAC on average outperforms the TX2 GPU by approximately 1.9× (or 7.5× with fabrication technology scaled) in energy consumption for image classification applications. On low power settings and within a margin of ∼3.7%--5.5% accuracy loss compared to ARM Cortex-A57 CPU implementation, BiNMAC is roughly ∼9.7×--17.2× (or 38.8×--68.8× with fabrication technology scaled) more energy efficient for physiological applications while meeting the application deadline.

Energy Harvesting From the Vibrations of Rotating Systems

2017 ◽  
Vol 140 (2) ◽  
Author(s):  
Christopher G. Cooley ◽  
Tan Chai
Keyword(s):  
Rotation Speed ◽  
Excitation Frequency ◽  
Average Power ◽  
Local Maximum ◽  
Operating Conditions ◽  
Centripetal Acceleration ◽  
Local Maxima ◽  
Closed Form Solutions ◽  
Energy Harvesters ◽  
Wide Range

This study investigates the vibration of and power harvested by typical electromagnetic and piezoelectric vibration energy harvesters when applied to vibrating host systems that rotate at constant speed. The governing equations for these electromechanically coupled devices are derived using Newtonian mechanics and Kirchhoff's voltage law. The natural frequency for these devices is speed-dependent due to the centripetal acceleration from their constant rotation. Resonance diagrams are used to identify excitation frequencies and speeds where these energy harvesters have large amplitude vibration and power harvested. Closed-form solutions are derived for the steady-state response and power harvested. These devices have multifrequency dynamic response due to the combined vibration and rotation of the host system. Multiple resonances are possible. The average power harvested over one oscillation cycle is calculated for a wide range of operating conditions. Electromagnetic devices have a local maximum in average harvested power that occurs near a specific excitation frequency and rotation speed. Piezoelectric devices, depending on their mechanical damping, can have two local maxima of average power harvested. Although these maxima are sensitive to small changes in the excitation frequency, they are much less sensitive to small changes in rotation speed.

Low power aware pulse triggered flip flops using modified clock gating approaches

2018 ◽  
Vol 15 (6) ◽  
pp. 792-803
Author(s):  
Sudhakar Jyothula
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Average Power ◽  
Essential Element ◽  
Battery Life ◽  
Portable Devices ◽  
Clock Gating ◽  
Flip Flop ◽  
Content Type ◽  
Low Leakage

PurposeThe purpose of this paper is to design a low power clock gating technique using Galeor approach by assimilated with replica path pulse triggered flip flop (RP-PTFF).Design/methodology/approachIn the present scenario, the inclination of battery for portable devices has been increasing tremendously. Therefore, battery life has become an essential element for portable devices. To increase the battery life of portable devices such as communication devices, these have to be made with low power requirements. Hence, power consumption is one of the main issues in CMOS design. To reap a low-power battery with optimum delay constraints, a new methodology is proposed by using the advantages of a low leakage GALEOR approach. By integrating the proposed GALEOR technique with conventional PTFFs, a reduction in power consumption is achieved.FindingsThe design was implemented in mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing conventional PTFFs in terms of power consumption. The average power consumed by the proposed technique (RP-PTFF clock gating with the GALEOR technique) is reduced to 47 per cent compared to conventional PTFF for 100 per cent switching activity.Originality/valueThe study demonstrates that RP-PTFF with clock gating using the GALEOR approach is a design that is superior to the conventional PTFFs.

A wide range delay locked loop for low power and low jitter applications

2017 ◽  
Vol 46 (3) ◽  
pp. 401-414 ◽  
Author(s):  
Motahhareh Estebsari ◽  
Mohammad Gholami ◽  
Mohammad Javad Ghahramanpour
Keyword(s):  
Low Power ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Low Jitter
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