Analysis of Main LC-VCO Parameters for Multistandard Tranceivers

This paper reviews CMOS LC Voltage Controlled Oscillators (VCO) for wireless multi-standard transceivers and wireless communications. The main parameters, such as IC technology, phase noise, carrier frequency, supply voltage, tuning range, power dissipation, figure of merit (FOMT and FOMTT) were reviewed in this paper. These parameters were taken of 20 articles published in 2012–2016 years. Of the reviewed articles it can be said that most VCOs was designed in 180 nm (55%) and 65 nm (25%) CMOS IC technology. FOMTT quality function has been proposed for extended VCO quality assessment. FOMTT quality function additionally evaluates VCO IC technology, and the power supply.

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DESIGN AND INVESTIGATION OF 65 NM RF CMOS TECHNOLOGY LC-VCO’S / AUKŠTADAŽNIŲ, 65 NM KMOP TECHNOLOGIJOS, LC ĮTAMPA VALDOMŲ GENERATORIŲ PROJEKTAVIMAS IR TYRIMAS

Mokslas - Lietuvos ateitis ◽

10.3846/mla.2014.29 ◽

2014 ◽

Vol 6 (2) ◽

pp. 198-201 ◽

Cited By ~ 2

Author(s):

Vytautas Mačaitis ◽

Vaidotas Barzdėnas

Keyword(s):

Power Dissipation ◽

Tuning Range ◽

Frequency Tuning ◽

Supply Voltage ◽

Cmos Technology ◽

Rf Cmos ◽

Voltage Controlled Oscillators ◽

Capacitor Array ◽

Layout Area ◽

Offset Frequency

In this paper, two LC Voltage-Controlled Oscillators (LC-LC-VCO1 and LC-VCO2) are designed using TSMC 65 nm LP/MS/RF CMOS technology. Two arrays, one of which is a 6-bit capacitor array and the other – an array of MOS varactors, provide a wide LC-VCO frequency tuning range. Post-layout simulation results unveiled that at 1.8 V supply voltage the tuning range of LC-VCO1 spans from 5.17 GHz to 6.76 GHz and for LC-VCO2 the range spans from 6.33 GHz to 8.08 GHz. The phase noise at 1 MHz offset frequency is about −123.1 dBc/Hz for LC-VCO1 and −121.6 dBc/Hz for LC-VCO2. The power dissipation at maximum carrier is 30.47 mW for LC-VCO1 and 30.5 mW for LC-VCO2. The layout area is 285×335 μm and 255×305 μm, respectively for LC-VCO1 and LC-VCO2. Straipsnyje nagrinėjami ir projektuojami LC įtampa valdomi generatoriai (LC-ĮVG), plačiai taikomi šiuolaikiniuose daugiastandarčiuose ir daugiajuosčiuose siųstuvuose-imtuvuose. Naudojant TSMC kompanijos 65 nm LP/MS/RF KMOP integrinių grandynų gamybos technologiją suprojektuoti ir išanalizuoti du skirtingų dažnio diapazonų LC-ĮVG. Generuojamas dažnis yra valdomas dviem būdais, t. y. galimas apytikslis bei tikslus dažnio nustatymas. Norint apytiksliai nustatyti dažnį naudojamas 6 bitais skaitmeniškai valdomas perjungiamų kondensatorių blokas, o norint tiksliai parinkti valdymą – NMOP varaktorių blokas. Kompiuterinio modeliavimo metu gauti tokie pagrindiniai LC-ĮVG parametrai: valdomo dažnio diapazonas – nuo 5,17 GHz iki 6,76 GHz (LC-ĮVG1) ir nuo 6,33 GHz iki 8,08 GHz (LC-ĮVG2); fazinis triukšmas, esant 1 MHz poslinkio dažniui ir maksimaliam nešlio dažniui: –123,1 dBc/Hz (LC-ĮVG1) ir –121,6 dBc/Hz (LC-ĮVG2); vartojamoji galia, esant maksimaliam nešlio dažniui: –30,47 mW (LC-ĮVG1) ir 30,5 mW (LC-ĮVG2). Suprojektuotų LC-ĮVG1 ir LC-ĮVG2 topologijų plotas yra atitinkamai lygus 0,078 mm2 ir 0,096 mm2.

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A Direct Bulk Coupling PMOS Colpitts QVCO Using Capacitive-Feedback Structure

Journal of Circuits System and Computers ◽

10.1142/s0218126619501251 ◽

2019 ◽

Vol 28 (08) ◽

pp. 1950125

Author(s):

Jianqun Ding ◽

Lijun Huang ◽

Xianwu Mi ◽

Dajiang He ◽

Shenghai Chen ◽

...

Keyword(s):

Power Dissipation ◽

Figure Of Merit ◽

Supply Voltage ◽

Voltage Controlled Oscillator ◽

Chip Area ◽

Low Power Dissipation ◽

Feedback Structure ◽

Voltage Swing ◽

Low Supply Voltage ◽

Capacitive Feedback

In this paper, a full PMOS Colpitts quadrature voltage-controlled oscillator (QVCO) topology, suitable for low supply voltage and low power dissipation, is presented. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed. Quadrature coupling is achieved by employing direct bulk coupling technique, leading to reduction in both power and chip area. The proposed QVCO covers a 5% tuning range between 2.325 GHz and 2.435 GHz, and the phase noise is [Formula: see text]128.2 dBc/Hz at 1-MHz offset from the 2.34-GHz carrier while consuming only 0.535 mW from 0.55-V supply voltage, yielding a figure-of-merit (FoM) of 198 dBc/Hz.

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Robust 12T Sram Cell Using 45nm Technology

International Journal of Scientific Research in Science Engineering and Technology ◽

10.32628/ijsrset207348 ◽

2020 ◽

pp. 170-174

Author(s):

N. Geetha Rani ◽

N. Jyothi ◽

P. Leelavathi ◽

P. Deepthi Swarupa Rani ◽

S. Reshma

Keyword(s):

Power Consumption ◽

Low Power ◽

Power Supply ◽

Power Dissipation ◽

Supply Voltage ◽

Leakage Power ◽

Sram Cell ◽

Static Power ◽

Low Supply Voltage ◽

Multi Core Processor

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

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A Novel Current-Controlled Oscillator-Based Low-Supply-Voltage Microbolometer Readout Architecture

Journal of Circuits System and Computers ◽

10.1142/s0218126620501698 ◽

2020 ◽

Vol 29 (10) ◽

pp. 2050169

Author(s):

Mehmet Ali Gülden ◽

Ertan Zencir ◽

Enver Çavuş

Keyword(s):

Power Supply ◽

Power Dissipation ◽

Supply Voltage ◽

Focal Plane Arrays ◽

Input Circuit ◽

Cmos Process ◽

Analog To Digital ◽

Lower Power ◽

Readout Circuits ◽

Low Supply Voltage

In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10–15[Formula: see text]pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach.

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