A Novel Current-Controlled Oscillator-Based Low-Supply-Voltage Microbolometer Readout Architecture

2020 ◽  
Vol 29 (10) ◽  
pp. 2050169
Author(s):  
Mehmet Ali Gülden ◽  
Ertan Zencir ◽  
Enver Çavuş
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Focal Plane Arrays ◽  
Input Circuit ◽  
Cmos Process ◽  
Analog To Digital ◽  
Lower Power ◽  
Readout Circuits ◽  
Low Supply Voltage

In this paper, we present a novel, almost-digital approach for bolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in the classical readout circuits. This approach, which has not been reported before, both produces the required gain in the bolometer input circuit and directly digitizes the bolometer signal. With the proposed architecture, the need for large capacitances (of the order of 10–15[Formula: see text]pF for each column) at which the current is accumulated in the bolometer circuits and the voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design readout circuits with reduced pixel pitch and lower power supply, both of which in turn lead to higher-resolution Focal Plane Arrays (FPAs) with lower power dissipation. The new architecture is modeled and simulated using a 180-nm CMOS process for sensitivity, noise performance, and power dissipation. Unlike the 3.3-V power supply usage of classical readout circuits, the proposed design utilizes 1.2-V analog and 0.9-V digital supply voltages with a power dissipation of almost half of the classical approach.

scholarly journals Robust 12T Sram Cell Using 45nm Technology

2020 ◽  
pp. 170-174
Author(s):  
N. Geetha Rani ◽  
N. Jyothi ◽  
P. Leelavathi ◽  
P. Deepthi Swarupa Rani ◽  
S. Reshma
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Sram Cell ◽  
Static Power ◽  
Low Supply Voltage ◽  
Multi Core Processor

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

scholarly journals Analysis of Main LC-VCO Parameters for Multistandard Tranceivers

2017 ◽  
Vol 9 (3) ◽  
pp. 324-328 ◽  
Author(s):  
Vytautas Mačaitis ◽  
Romualdas Navickas
Keyword(s):  
Power Supply ◽  
Carrier Frequency ◽  
Power Dissipation ◽  
Figure Of Merit ◽  
Tuning Range ◽  
Supply Voltage ◽  
Quality Function ◽  
Voltage Controlled Oscillators ◽  
Cmos Ic ◽  
Ic Technology

This paper reviews CMOS LC Voltage Controlled Oscillators (VCO) for wireless multi-standard transceivers and wireless communications. The main parameters, such as IC technology, phase noise, carrier frequency, supply voltage, tuning range, power dissipation, figure of merit (FOMT and FOMTT) were reviewed in this paper. These parameters were taken of 20 articles published in 2012–2016 years. Of the reviewed articles it can be said that most VCOs was designed in 180 nm (55%) and 65 nm (25%) CMOS IC technology. FOMTT quality function has been proposed for extended VCO quality assessment. FOMTT quality function additionally evaluates VCO IC technology, and the power supply.

A Direct Bulk Coupling PMOS Colpitts QVCO Using Capacitive-Feedback Structure

2019 ◽  
Vol 28 (08) ◽  
pp. 1950125
Author(s):  
Jianqun Ding ◽  
Lijun Huang ◽  
Xianwu Mi ◽  
Dajiang He ◽  
Shenghai Chen ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Low Power Dissipation ◽  
Feedback Structure ◽  
Voltage Swing ◽  
Low Supply Voltage ◽  
Capacitive Feedback

In this paper, a full PMOS Colpitts quadrature voltage-controlled oscillator (QVCO) topology, suitable for low supply voltage and low power dissipation, is presented. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed. Quadrature coupling is achieved by employing direct bulk coupling technique, leading to reduction in both power and chip area. The proposed QVCO covers a 5% tuning range between 2.325 GHz and 2.435 GHz, and the phase noise is [Formula: see text]128.2 dBc/Hz at 1-MHz offset from the 2.34-GHz carrier while consuming only 0.535 mW from 0.55-V supply voltage, yielding a figure-of-merit (FoM) of 198 dBc/Hz.

A High-Order CMOS Bandgap Voltage Reference

2014 ◽  
Vol 989-994 ◽  
pp. 1165-1168
Author(s):  
Qian Neng Zhou ◽  
Yun Song Li ◽  
Jin Zhao Lin ◽  
Hong Juan Li ◽  
Chen Li ◽  
...  
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
High Order ◽  
Cmos Process ◽  
Voltage Reference ◽  
Power Supply Voltage ◽  
Power Supply Rejection Ratio ◽  
Voltage Deviation ◽  
Bandgap Voltage Reference

A high-order bandgap voltage reference (BGR) is designed by adopting a current which is proportional to absolute temperature T1.5. The high-order BGR is analyzed and simulated in SMIC 0.18μm CMOS process. Simulation results show that the designed high-order BGR achieves temperature coefficient of 2.54ppm/°C when temperature ranging from-55°C to 125°C. The high-order BGR at 10Hz, 100Hz, 1kHz, 10kHz and 100kHz achieves, respectively, the power supply rejection ratio of-64.01dB, -64.01dB, -64dB, -63.5dB and-53.2dB. When power supply voltage changes from 1.7V to 2.5V, the output voltage deviation of BGR is only 617.6μV.

A New Small-Sized Non-Dispersive Infrared (NDIR) Sensor and its Drive/Readout Circuits

2016 ◽  
Author(s):  
Paul C.-P. Chao ◽  
Li-Chi Hsu ◽  
Trong-Hieu Tran
Keyword(s):  
Pulse Width Modulation ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Analog To Digital ◽  
Readout Circuits ◽  
Low Pass ◽  
Driver Circuit ◽  
Module Size ◽  
Gas Chamber

A new miniaturized, non-dispersive, infrared (NDIR) sensor for CO2 intended to be installed in mobile phones and its drive/readout circuits are presented in this study. A typical NDIR sensor consists of three main components; an infrared (IR) light-emitter (light source), a gas chamber, a photo detector (PD) light receiver) and the associated drive/readout circuits. The geometry of the gas chamber is optimized to minimize the total module size to approximately 10 mm × 5 mm × 5 mm, which is much smaller than commercially-available gas sensors. Driver and readout circuits are successfully designed and taped out. The driver circuit intends to generate pulse width modulation (PWM) signal to control proper dimming of LED. The readout circuit, which acquires small signal from photo detector then converts to digital values, includes amplifier, low pass filter and analog-to-digital converter (ADC). The proposed circuit is fabricated by the TSMC 0.35-μm CMOS process, where the area is 4.527 mm2 while power consumption is 60.16 mW for the whole chip. The resolution is less than 12 ppm along with time constant is 0.1 sec.

Single Inductor Bipolar Outputs DC-DC Converter with Current Mode Control Circuit

2013 ◽  
Vol 534 ◽  
pp. 220-226 ◽  
Author(s):  
Nobukazu Takai ◽  
Takashi Okada ◽  
Kenji Takahashi ◽  
Hajime Yokoo ◽  
Shunsuke Miwa ◽  
...  
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Process ◽  
Power Supply Voltage ◽  
Negative Power ◽  
Current Mode Control ◽  
Mode Control ◽  
Digital Still Camera ◽  
Simulation Results

Mobile equipment such as organic-EL display, digital still camera and so on re-quire both positive and negative power supply voltage to obtain high quality. Single InductorMultiple-Output (SIMO) DC-DC converter can provide a pair of positive and negative outputvoltages with only one external inductor. This paper describes SIMO DC-DC Converter usingproposed current-mode control (CMC) circuit. The proposed CMC circuit realizes high responsespeed for the change of load current. Spectre simulations with 0.18m CMOS process parameterare performed to verify the validity of the proposed converter. The simulation results indicatethat the proposed converter has higher response time compared with conventional converter.

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

scholarly journals Development of a functional model of the temperature meter

2021 ◽  
pp. 53-59
Author(s):  
Natalia Zaschepkina ◽  
Maxim Svyta
Keyword(s):  
Power Supply ◽  
Temperature Sensor ◽  
Supply Voltage ◽  
Functional Model ◽  
Measurement Range ◽  
Platinum Resistance ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Operating Range

Thin-film platinum resistance thermometers of various designs and performance are widely used in various industries. The temperature measurement range of these sensors is from -200 °C to +600 °C. A functional model of a portable digital temperature meter in the range from -50 °C to +300 ℃ based on the L416 sensor type Pt100 is proposed. The optimal circuit solution for connecting the L416 sensor to the Winston measuring bridge was selected. The proposed circuit solution is suitable for power supply from autonomous DC sources, which allows for miniaturization of the device and contributes to energy efficiency. The amplification of the output voltage of the amplifier in the entire operating range of the analog-to-digital converter following the operating range of the temperature sensor has been performed, which allows obtaining the maximum resolution of the analog-to-digital conversion when measuring temperature. A functional model for converting the resistance of a temperature sensor into a digital code has been developed. The functional model shows that the source code of the analog-to-digital converter does not depend on the supply voltage of the circuit, thus realizing the stability of the function of converting the resistance of the sensor into the value of the code of the analog-to-digital converter. The sensor has a normalized characteristic of the dependence of resistance on temperature, so a precision resistance box MSR-60M has been used to calibrate the circuit of the temperature meter. With the help of the resistance box MSR-60M, it is possible to calibrate the circuit of the temperature meter with an uncertainty of 0.07 °C. Keywords: temperature meter; RTD; Pt100; Winston bridge; ratiometric power supply.

High-Swing, High-Resolution, Low-Power, Low-Area Voltage-Mode LTA/WTA Circuits

2015 ◽  
Vol 24 (07) ◽  
pp. 1550103 ◽  
Author(s):  
Mohammad Soleimani ◽  
Siroos Toofan ◽  
Mostafa Yargholi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Rank Order ◽  
Active Area ◽  
Total Power ◽  
Common Source ◽  
Cmos Process ◽  
Process Technology

In this paper, a general architecture for analog implementation of loser/winner-take-all (LTA/WTA) and other rank order circuits is presented. This architecture is composed of a differential amplifier with merged n-inputs and a merged common-source with active load (MCSAL) circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.

scholarly journals A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Nabihah Ahmad ◽  
Rezaul Hasan
Keyword(s):  
Circuit Design ◽  
Power Dissipation ◽  
Low Voltage ◽  
Supply Voltage ◽  
Propagation Delay ◽  
Cmos Process ◽  
Xor Gate ◽  
Power Efficient ◽  
Pass Transistor ◽  
Full Swing

A power efficient circuit topology is proposed to implement a low-voltage CMOS 2-input pass-transistor XOR gate. This design aims to minimize power dissipation and reduce transistor count while at the same time reducing the propagation delay. The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs.

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